| /netbsd-src/external/gpl3/binutils/dist/opcodes/ |
| H A D | i386-opc.tbl | 36 #define Reg64 Class=Reg|Qword
187 …perandSize|Modrm|No_sSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspec…
191 …uf|HLEPrefixRelease|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIn…
192 mov, 0xb8, x64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|Optimize, { Imm64, Reg64 }
193 movabs, 0xb8, x64, No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Imm64, Reg64 }
199 mov, 0x8c, 0, RegMem|No_bSuf|No_sSuf|NoRex64, { SReg, Reg16|Reg32|Reg64 }
201 mov, 0x8e, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, SReg }
205 mov, 0xf20, x64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Control, Reg64 }
207 mov, 0xf21, x64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Debug, Reg64 }
211 …drm|CheckOperandSize|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
[all …]
|
| H A D | ChangeLog-2008 | 479 into 32bit and 64bit. Remove Reg64|Qword and add
|
| H A D | ChangeLog-2019 | 606 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
825 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
|
| H A D | ChangeLog-2013 | 223 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
|
| H A D | ChangeLog-2007 | 825 (Reg64): Likewise.
|
| /netbsd-src/external/gpl3/binutils.old/dist/opcodes/ |
| H A D | i386-opc.tbl | 32 #define Reg64 Class=Reg|Qword
134 …e|Modrm|No_sSuf|No_ldSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|W…
135 …|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|HLEPrefixRelease, { Reg64, Reg64|Unspecified|Qwo…
139 …uf|HLEPrefixRelease|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qw…
140 …Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|HLEPrefixRelease|Optimize, { Imm32S, Reg64|Qword|Unspecified|…
141 mov, 0xb8, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Optimize, { Imm64, Reg64 }
142 movabs, 0xb8, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Imm64, Reg64 }
143 …b8, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Imm64, Reg64 }
149 mov, 0x8c, None, 0, RegMem|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { SReg, Reg16|Reg32|Reg64 }
151 …x8c, None, Cpu64, D|RegMem|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Reg64 }
[all …]
|
| H A D | ChangeLog-2008 | 479 into 32bit and 64bit. Remove Reg64|Qword and add
|
| H A D | ChangeLog-2019 | 606 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
825 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
|
| H A D | ChangeLog-2013 | 223 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
|
| H A D | ChangeLog-2007 | 825 (Reg64): Likewise.
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 214 const Register Reg64 = MI->getOperand(0).getReg(); in expandLoadStackGuard() local
215 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32); in expandLoadStackGuard()
223 .addReg(Reg64, RegState::ImplicitDefine); in expandLoadStackGuard()
226 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64) in expandLoadStackGuard()
227 .addReg(Reg64) in expandLoadStackGuard()
237 MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0); in expandLoadStackGuard()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 539 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
547 def "64" : RegisterOperand<Reg64, "printImplicitlyTypedVectorList"> {
565 def "8b" : TypedVecListRegOperand<Reg64, 8, "b"> {
571 def "4h" : TypedVecListRegOperand<Reg64, 4, "h"> {
577 def "2s" : TypedVecListRegOperand<Reg64, 2, "s"> {
583 def "1d" : TypedVecListRegOperand<Reg64, 1, "d"> {
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| H A D | AArch64FastISel.cpp | 1859 unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass); in emitLoad() local
1861 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emitLoad()
1865 ResultReg = Reg64; in emitLoad()
3934 Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in emiti1Ext() local
3936 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emiti1Ext()
3940 ResultReg = Reg64; in emiti1Ext()
4454 unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass); in optimizeIntExtLoad() local
4456 TII.get(AArch64::SUBREG_TO_REG), Reg64) in optimizeIntExtLoad()
4460 Reg = Reg64; in optimizeIntExtLoad()
|
| /netbsd-src/external/gpl3/gdb/dist/opcodes/ |
| H A D | ChangeLog-2008 | 479 into 32bit and 64bit. Remove Reg64|Qword and add
|
| H A D | ChangeLog-2019 | 606 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
825 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
|
| H A D | ChangeLog-2013 | 223 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
|
| H A D | ChangeLog-2007 | 825 (Reg64): Likewise.
|
| /netbsd-src/external/gpl3/gdb.old/dist/opcodes/ |
| H A D | ChangeLog-2008 | 479 into 32bit and 64bit. Remove Reg64|Qword and add
|
| H A D | ChangeLog-2019 | 606 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
825 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
|
| H A D | ChangeLog-2013 | 223 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
|
| H A D | ChangeLog-2007 | 825 (Reg64): Likewise.
|
| /netbsd-src/external/gpl3/binutils/dist/gas/ |
| H A D | ChangeLog-2004 | 1472 (parse_register): Disallow Reg64 registers in 32-bit mode.
|
| H A D | ChangeLog-2007 | 1177 DWORD memory to Reg64 in Intel synax.
|
| /netbsd-src/external/gpl3/binutils.old/dist/gas/ |
| H A D | ChangeLog-2004 | 1472 (parse_register): Disallow Reg64 registers in 32-bit mode.
|
| H A D | ChangeLog-2007 | 1177 DWORD memory to Reg64 in Intel synax.
|