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Searched refs:RS (Results 1 – 25 of 568) sorted by relevance

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/netbsd-src/external/gpl3/gdb/dist/sim/mips/
H A Dmips3264r6.igen18 110110,5.RS!0,21.OFFSET:POOL32X:32::BEQZC
19 "beqzc r<RS>, <OFFSET>"
23 if (GPR[RS] == 0)
37 111110,5.RS!0,21.OFFSET:POOL32X:32::BNEZC
38 "bnezc r<RS>, <OFFSET>"
42 if (GPR[RS] != 0)
57 010110,5.RS,5.RT,16.OFFSET:POOL32X:32::B1xxC
58 "blezc r<RT>, <OFFSET>": RS==0&&RT!=0
59 "bgezc r<RT>, <OFFSET>":RS!=0&&RS==RT
60 "bgec r<RS>, r<RT>, <OFFSET>"
[all …]
H A Dvr.igen24 // LHS (+/-) GPR[RS] * GPR[RT]
30 // - RS are RT are the multiplication source registers
38 // - SHORT_P is true if RS and RT must be 16-bit numbers.
105 000000,5.RS,5.RT,00000,00000,101000::32::MADD16
106 "madd16 r<RS>, r<RT>"
109 do_vr_mul_op (SD_, 0, RS, RT,
119 000000,5.RS,5.RT,00000,00000,101001::64::DMADD16
120 "dmadd16 r<RS>, r<RT>"
123 do_vr_mul_op (SD_, 0, RS, RT,
137 000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101001::64::DMACC
[all …]
H A Dtx.igen6 011100,5.RS,5.RT,5.RD,00000000000:MMINORM:::MADD
7 "madd r<RS>, r<RT>":RD == 0
8 "madd r<RD>, r<RS>, r<RT>"
13 * (int64_t) EXTEND32 (GPR[RS])));
15 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
24 011100,5.RS,5.RT,5.RD,00000000001:MMINORM:::MADDU
25 "maddu r<RS>, r<RT>":RD == 0
26 "maddu r<RD>, r<RS>, r<RT>"
30 + ((uint64_t) VL4_8 (GPR[RS])
33 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
/netbsd-src/tests/compat/linux/
H A Dh_inotify_watch_change.c47 RS(targetfd = open("test", LINUX_O_RDWR|LINUX_O_CREAT, 0644)); in _start()
48 RS(close(targetfd)); in _start()
50 RS(fd = syscall(LINUX_SYS_inotify_init)); in _start()
51 RS(wd = syscall(LINUX_SYS_inotify_add_watch, fd, (register_t)"test", in _start()
55 RS(targetfd = open("test", LINUX_O_RDONLY|LINUX_O_CREAT, 0644)); in _start()
56 RS(close(targetfd)); in _start()
58 RS(nread = read(fd, events, sizeof(events))); in _start()
63 RS(wd = syscall(LINUX_SYS_inotify_add_watch, fd, (register_t)"test", in _start()
67 RS(targetfd = open("test", LINUX_O_RDONLY|LINUX_O_CREAT, 0644)); in _start()
68 RS(close(targetfd)); in _start()
[all …]
H A Dh_inotify_single_file.c51 RS(targetfd = open("test", LINUX_O_RDWR|LINUX_O_CREAT, 0644)); in _start()
52 RS(close(targetfd)); in _start()
54 RS(fd = syscall(LINUX_SYS_inotify_init)); in _start()
55 RS(wd = syscall(LINUX_SYS_inotify_add_watch, fd, (register_t)"test", in _start()
59 RS(targetfd = open("test", LINUX_O_RDWR|LINUX_O_CREAT, 0644)); in _start()
60 RS(write(targetfd, &buf, sizeof(buf))); in _start()
61 RS(read(targetfd, &buf, sizeof(buf))); in _start()
62 RS(close(targetfd)); in _start()
63 RS(targetfd = open("test", LINUX_O_RDONLY|LINUX_O_CREAT, 0644)); in _start()
64 RS(close(targetfd)); in _start()
[all …]
H A Dh_inotify_directory.c69 RS(mkdir("test", 0644)); in _start()
71 RS(fd = syscall(LINUX_SYS_inotify_init)); in _start()
72 RS(wd = syscall(LINUX_SYS_inotify_add_watch, fd, (register_t)"test", in _start()
76 RS(targetfd = open("test/test", LINUX_O_RDWR|LINUX_O_CREAT, 0644)); in _start()
77 RS(write(targetfd, &targetfd, sizeof(targetfd))); in _start()
78 RS(close(targetfd)); in _start()
79 RS(rename("test/test", "test/test2")); in _start()
80 RS(unlink("test/test2")); in _start()
81 RS(rename("test", "test2")); in _start()
82 RS(rmdir("test2")); in _start()
[all …]
H A Dh_inotify_init.c47 RS(fd = syscall(LINUX_SYS_inotify_init)); in _start()
50 RS(close(fd)); in _start()
53 RS(fd = syscall(LINUX_SYS_inotify_init1, LINUX_IN_NONBLOCK)); in _start()
56 RS(close(fd)); in _start()
59 RS(fd = syscall(LINUX_SYS_inotify_init1, LINUX_IN_CLOEXEC)); in _start()
62 RS(close(fd)); in _start()
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Diq2000-opc.c249 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
261 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
273 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
285 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
297 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
309 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
321 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
333 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
345 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
357 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
[all …]
H A Dxstormy16-opc.c215 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ')', 0 } },
221 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ')', 0 } },
227 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ')', 0 } },
233 { { MNEM, OP (WS2), ' ', '(', OP (RS), ')', ',', OP (RDM), 0 } },
239 { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ')', ',', OP (RDM), 0 } },
245 { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ')', ',', OP (RDM), 0 } },
251 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ',', OP (IMM12), ')', 0 } },
257 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ',', OP (IMM12), ')', 0 } },
263 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ',', OP (IMM12), ')', 0 } },
269 { { MNEM, OP (WS2), ' ', '(', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
[all …]
H A Dppc-opc.c3398 #define RS RC + 1 macro
3399 #define RT RS
3401 #define RD RS
3404 #define RD_EVEN RS + 1
5305 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5308 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
5310 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, EXT, {RS, RB, RA}},
5311 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5314 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, EXT, {RS, RB, UIMM}},
5315 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Diq2000-opc.c249 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
261 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
273 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
285 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
297 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
309 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
321 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
333 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
345 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
357 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
[all …]
H A Dxstormy16-opc.c215 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ')', 0 } },
221 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ')', 0 } },
227 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ')', 0 } },
233 { { MNEM, OP (WS2), ' ', '(', OP (RS), ')', ',', OP (RDM), 0 } },
239 { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ')', ',', OP (RDM), 0 } },
245 { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ')', ',', OP (RDM), 0 } },
251 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ',', OP (IMM12), ')', 0 } },
257 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ',', OP (IMM12), ')', 0 } },
263 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ',', OP (IMM12), ')', 0 } },
269 { { MNEM, OP (WS2), ' ', '(', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
[all …]
H A Dppc-opc.c3319 #define RS RC + 1 macro
3320 #define RT RS
3322 #define RD RS
3325 #define RD_EVEN RS + 1
5126 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5129 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
5131 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5132 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
5135 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
5136 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
H A DResourceManager.cpp105 getStrategyFor(const ResourceState &RS) { in getStrategyFor() argument
106 if (RS.isAResourceGroup() || RS.getNumUnits() > 1) in getStrategyFor()
107 return std::make_unique<DefaultResourceStrategy>(RS.getReadyMask()); in getStrategyFor()
138 const ResourceState &RS = *Resources[Index]; in ResourceManager() local
139 if (!RS.isAResourceGroup()) { in ResourceManager()
180 ResourceState &RS = *Resources[Index]; in selectPipe() local
181 assert(RS.isReady() && "No available units to select!"); in selectPipe()
185 if (!RS.isAResourceGroup() && RS.getNumUnits() == 1) in selectPipe()
186 return std::make_pair(ResourceID, RS.getReadyMask()); in selectPipe()
188 uint64_t SubResourceID = Strategies[Index]->select(RS.getReadyMask()); in selectPipe()
[all …]
H A DRegisterFile.cpp356 bool RegisterFile::canEliminateMove(const WriteState &WS, const ReadState &RS, in canEliminateMove() argument
358 const RegisterMapping &RMFrom = RegisterMappings[RS.getRegisterID()]; in canEliminateMove()
394 bool IsZeroMove = ZeroRegisters[RS.getRegisterID()]; in canEliminateMove()
422 const ReadState &RS = Reads[I]; in tryEliminateMoveOrSwap() local
424 if (!canEliminateMove(WS, RS, RegisterFileIndex)) in tryEliminateMoveOrSwap()
429 ReadState &RS = Reads[I]; in tryEliminateMoveOrSwap() local
432 const RegisterMapping &RMFrom = RegisterMappings[RS.getRegisterID()]; in tryEliminateMoveOrSwap()
439 RRIFrom.RenameAs ? RRIFrom.RenameAs : RS.getRegisterID(); in tryEliminateMoveOrSwap()
450 if (ZeroRegisters[RS.getRegisterID()]) { in tryEliminateMoveOrSwap()
452 RS.setReadZero(); in tryEliminateMoveOrSwap()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/FuzzMutate/
H A DIRMutator.cpp39 auto RS = makeSampler<Function *>(IB.Rand); in mutate() local
42 RS.sample(&F, /*Weight=*/1); in mutate()
43 mutate(*RS.getSelection(), IB); in mutate()
61 auto RS = makeSampler<IRMutationStrategy *>(IB.Rand); in mutateModule() local
63 RS.sample(Strategy.get(), in mutateModule()
64 Strategy->getWeight(CurSize, MaxSize, RS.totalWeight())); in mutateModule()
65 auto Strategy = RS.getSelection(); in mutateModule()
100 auto RS = makeSampler(IB.Rand, make_filter_range(Operations, OpMatchesPred)); in chooseOperation() local
101 if (RS.isEmpty()) in chooseOperation()
103 return *RS; in chooseOperation()
[all …]
H A DRandomIRBuilder.cpp33 auto RS = makeSampler(Rand, make_filter_range(Insts, MatchesPred)); in findOrCreateSource() local
35 RS.sample(nullptr, /*Weight=*/1); in findOrCreateSource()
36 if (Instruction *Src = RS.getSelection()) in findOrCreateSource()
44 auto RS = makeSampler<Value *>(Rand); in newSource() local
45 RS.sample(Pred.generate(Srcs, KnownTypes)); in newSource()
61 RS.sample(NewLoad, RS.totalWeight()); in newSource()
66 assert(!RS.isEmpty() && "Failed to generate sources"); in newSource()
67 return RS.getSelection(); in newSource()
97 auto RS = makeSampler<Use *>(Rand); in connectToSink() local
106 RS.sample(&U, 1); in connectToSink()
[all …]
/netbsd-src/external/gpl3/gdb/dist/cpu/
H A Diq10.cpu27 (dni andoui-q10 "iq10 and upper ones immediate" (MACH10 USES-RS USES-RT)
33 (dni andoui2-q10 "iq10 and upper ones immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT)
39 (dni orui-q10 "or upper immediate" (MACH10 USES-RS USES-RT)
45 (dni orui2-q10 "or upper immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT)
51 (dni mrgbq10 "merge bytes" (MACH10 USES-RD USES-RS USES-RT)
70 (dni mrgbq102 "merge bytes" (ALIAS NO-DIS MACH10 USES-RD USES-RS USES-RT)
122 (dni bbil "branch bit immediate likely" (MACH10 USES-RS)
130 (dni bbinl "branch bit immediate negated likely" (MACH10 USES-RS)
138 (dni bbvl "branch bit variable likely" (MACH10 USES-RS USES-RT)
146 (dni bbvnl "branch bit variable negated likely" (MACH10 USES-RS USES-RT)
[all …]
/netbsd-src/external/gpl3/binutils/dist/cpu/
H A Diq10.cpu27 (dni andoui-q10 "iq10 and upper ones immediate" (MACH10 USES-RS USES-RT)
33 (dni andoui2-q10 "iq10 and upper ones immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT)
39 (dni orui-q10 "or upper immediate" (MACH10 USES-RS USES-RT)
45 (dni orui2-q10 "or upper immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT)
51 (dni mrgbq10 "merge bytes" (MACH10 USES-RD USES-RS USES-RT)
70 (dni mrgbq102 "merge bytes" (ALIAS NO-DIS MACH10 USES-RD USES-RS USES-RT)
122 (dni bbil "branch bit immediate likely" (MACH10 USES-RS)
130 (dni bbinl "branch bit immediate negated likely" (MACH10 USES-RS)
138 (dni bbvl "branch bit variable likely" (MACH10 USES-RS USES-RT)
146 (dni bbvnl "branch bit variable negated likely" (MACH10 USES-RS USES-RT)
[all …]
H A Diq2000.cpu450 (dni add2 "add registers" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
456 (dni add "add registers" (USES-RD USES-RS USES-RT)
463 (dni addi2 "add immediate" (ALIAS NO-DIS USES-RS USES-RT)
469 (dni addi "add immediate" (USES-RS USES-RT)
475 (dni addiu2 "add immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT)
481 (dni addiu "add immediate unsigned" (USES-RS USES-RT)
487 (dni addu2 "add unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
493 (dni addu "add unsigned" (USES-RD USES-RS USES-RT)
499 (dni ado162 "add 16, ones complement" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
508 (dni ado16 "add 16, ones complement" (USES-RD USES-RS USES-RT)
[all …]
/netbsd-src/external/gpl3/gdb.old/dist/cpu/
H A Diq10.cpu27 (dni andoui-q10 "iq10 and upper ones immediate" (MACH10 USES-RS USES-RT)
33 (dni andoui2-q10 "iq10 and upper ones immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT)
39 (dni orui-q10 "or upper immediate" (MACH10 USES-RS USES-RT)
45 (dni orui2-q10 "or upper immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT)
51 (dni mrgbq10 "merge bytes" (MACH10 USES-RD USES-RS USES-RT)
70 (dni mrgbq102 "merge bytes" (ALIAS NO-DIS MACH10 USES-RD USES-RS USES-RT)
122 (dni bbil "branch bit immediate likely" (MACH10 USES-RS)
130 (dni bbinl "branch bit immediate negated likely" (MACH10 USES-RS)
138 (dni bbvl "branch bit variable likely" (MACH10 USES-RS USES-RT)
146 (dni bbvnl "branch bit variable negated likely" (MACH10 USES-RS USES-RT)
[all …]
H A Diq2000.cpu450 (dni add2 "add registers" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
456 (dni add "add registers" (USES-RD USES-RS USES-RT)
463 (dni addi2 "add immediate" (ALIAS NO-DIS USES-RS USES-RT)
469 (dni addi "add immediate" (USES-RS USES-RT)
475 (dni addiu2 "add immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT)
481 (dni addiu "add immediate unsigned" (USES-RS USES-RT)
487 (dni addu2 "add unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
493 (dni addu "add unsigned" (USES-RD USES-RS USES-RT)
499 (dni ado162 "add 16, ones complement" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
508 (dni ado16 "add 16, ones complement" (USES-RD USES-RS USES-RT)
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/cpu/
H A Diq10.cpu27 (dni andoui-q10 "iq10 and upper ones immediate" (MACH10 USES-RS USES-RT)
33 (dni andoui2-q10 "iq10 and upper ones immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT)
39 (dni orui-q10 "or upper immediate" (MACH10 USES-RS USES-RT)
45 (dni orui2-q10 "or upper immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT)
51 (dni mrgbq10 "merge bytes" (MACH10 USES-RD USES-RS USES-RT)
70 (dni mrgbq102 "merge bytes" (ALIAS NO-DIS MACH10 USES-RD USES-RS USES-RT)
122 (dni bbil "branch bit immediate likely" (MACH10 USES-RS)
130 (dni bbinl "branch bit immediate negated likely" (MACH10 USES-RS)
138 (dni bbvl "branch bit variable likely" (MACH10 USES-RS USES-RT)
146 (dni bbvnl "branch bit variable negated likely" (MACH10 USES-RS USES-RT)
[all …]
H A Diq2000.cpu450 (dni add2 "add registers" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
456 (dni add "add registers" (USES-RD USES-RS USES-RT)
463 (dni addi2 "add immediate" (ALIAS NO-DIS USES-RS USES-RT)
469 (dni addi "add immediate" (USES-RS USES-RT)
475 (dni addiu2 "add immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT)
481 (dni addiu "add immediate unsigned" (USES-RS USES-RT)
487 (dni addu2 "add unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
493 (dni addu "add unsigned" (USES-RD USES-RS USES-RT)
499 (dni ado162 "add 16, ones complement" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
508 (dni ado16 "add 16, ones complement" (USES-RD USES-RS USES-RT)
[all …]
/netbsd-src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/
H A DMIGChecker.cpp90 void checkReturnAux(const ReturnStmt *RS, CheckerContext &C) const;
101 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const { in checkPreStmt() argument
102 checkReturnAux(RS, C); in checkPreStmt()
104 void checkEndFunction(const ReturnStmt *RS, CheckerContext &C) const { in checkEndFunction() argument
105 checkReturnAux(RS, C); in checkEndFunction()
247 void MIGChecker::checkReturnAux(const ReturnStmt *RS, CheckerContext &C) const { in checkReturnAux() argument
264 if (!RS) in checkReturnAux()
271 SVal V = C.getSVal(RS); in checkReturnAux()
286 R->addRange(RS->getSourceRange()); in checkReturnAux()
287 bugreporter::trackExpressionValue(N, RS->getRetValue(), *R, in checkReturnAux()

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