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Searched refs:REG_UPDATE (Results 1 – 25 of 61) sorted by relevance

123

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_mmhubbub.c88 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, params->swlock); in mmhubbub2_config_mcif_buf()
91 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub2_config_mcif_buf()
92 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub2_config_mcif_buf()
94 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, 0); in mmhubbub2_config_mcif_buf()
97 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub2_config_mcif_buf()
98 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub2_config_mcif_buf()
100 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, 0); in mmhubbub2_config_mcif_buf()
103 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub2_config_mcif_buf()
104 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub2_config_mcif_buf()
106 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, 0); in mmhubbub2_config_mcif_buf()
[all …]
H A Damdgpu_dcn20_dwb.c88 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 1); in dwb2_config_dwb_cnv()
89 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_X, params->cnv_params.crop_x); in dwb2_config_dwb_cnv()
90 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_Y, params->cnv_params.crop_y); in dwb2_config_dwb_cnv()
91 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, params->cnv_params.crop_width); in dwb2_config_dwb_cnv()
92 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, params->cnv_params.crop_height); in dwb2_config_dwb_cnv()
94 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 0); in dwb2_config_dwb_cnv()
98 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_RATE, params->capture_rate); in dwb2_config_dwb_cnv()
101 REG_UPDATE(CNV_MODE, CNV_OUT_BPC, params->cnv_params.cnv_out_bpc); in dwb2_config_dwb_cnv()
123 REG_UPDATE(WB_ENABLE, WB_ENABLE, 1); in dwb2_enable()
132 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE); in dwb2_enable()
[all …]
H A Damdgpu_dcn20_stream_encoder.c88 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc2_update_hdmi_info_packet()
95 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc2_update_hdmi_info_packet()
102 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc2_update_hdmi_info_packet()
109 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc2_update_hdmi_info_packet()
116 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc2_update_hdmi_info_packet()
123 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc2_update_hdmi_info_packet()
130 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc2_update_hdmi_info_packet()
137 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc2_update_hdmi_info_packet()
156 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); in enc2_stream_encoder_update_hdmi_info_packets()
230 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 1); in enc2_update_gsp7_128_info_packet()
[all …]
H A Damdgpu_dcn20_dpp.c86 REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0); in dpp2_power_on_obuf()
88 REG_UPDATE(OBUF_MEM_PWR_CTRL, in dpp2_power_on_obuf()
91 REG_UPDATE(DSCL_MEM_PWR_CTRL, in dpp2_power_on_obuf()
127 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp2_cnv_setup()
128 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp2_cnv_setup()
129 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp2_cnv_setup()
130 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp2_cnv_setup()
216 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); in dpp2_cnv_setup()
217 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); in dpp2_cnv_setup()
218 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp2_cnv_setup()
[all …]
H A Damdgpu_dcn20_optc.c60 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, in optc2_enable_crtc()
64 REG_UPDATE(CONTROL, in optc2_enable_crtc()
91 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, in optc2_set_timing_db_mode()
124 REG_UPDATE(OTG_GSL_CONTROL, in optc2_use_gsl_as_master_update_lock()
167 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
170 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
173 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
204 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, in optc2_set_dsc_config()
210 REG_UPDATE(OPTC_WIDTH_CONTROL, in optc2_set_dsc_config()
233 REG_UPDATE(OTG_H_TIMING_CNTL, in optc2_set_odm_bypass()
[all …]
H A Damdgpu_dcn20_dwb_scl.c756 REG_UPDATE(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, h_ratio_luma); in dwb_program_horz_scalar()
759 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, h_taps_luma - 1); in dwb_program_horz_scalar()
760 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, h_taps_chroma - 1); in dwb_program_horz_scalar()
782 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, h_init_phase_luma_int); in dwb_program_horz_scalar()
783 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, h_init_phase_luma_frac); in dwb_program_horz_scalar()
784 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, h_init_phase_chroma_int); in dwb_program_horz_scalar()
785 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, h_init_phase_chroma_frac); in dwb_program_horz_scalar()
834 REG_UPDATE(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, v_ratio_luma); in dwb_program_vert_scalar()
837 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, v_taps_luma - 1); in dwb_program_vert_scalar()
838 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, v_taps_chroma - 1); in dwb_program_vert_scalar()
[all …]
H A Damdgpu_dcn20_hubp.c194 REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value); in hubp2_vready_at_or_After_vsync()
203 REG_UPDATE(HUBPRET_CONTROL, in hubp2_program_requestor()
445 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp2_program_pixel_format()
449 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp2_program_pixel_format()
454 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp2_program_pixel_format()
460 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp2_program_pixel_format()
464 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp2_program_pixel_format()
469 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp2_program_pixel_format()
474 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp2_program_pixel_format()
478 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp2_program_pixel_format()
[all …]
H A Damdgpu_dcn20_hubbub.c420 REG_UPDATE(DCN_VM_FB_LOCATION_TOP, in hubbub2_update_dchub()
423 REG_UPDATE(DCN_VM_FB_LOCATION_BASE, in hubbub2_update_dchub()
427 REG_UPDATE(DCN_VM_AGP_BASE, in hubbub2_update_dchub()
432 REG_UPDATE(DCN_VM_AGP_BOT, in hubbub2_update_dchub()
437 REG_UPDATE(DCN_VM_AGP_TOP, in hubbub2_update_dchub()
445 REG_UPDATE(DCN_VM_AGP_BASE, in hubbub2_update_dchub()
450 REG_UPDATE(DCN_VM_AGP_BOT, in hubbub2_update_dchub()
455 REG_UPDATE(DCN_VM_AGP_TOP, in hubbub2_update_dchub()
463 REG_UPDATE(DCN_VM_AGP_BASE, in hubbub2_update_dchub()
468 REG_UPDATE(DCN_VM_AGP_BOT, in hubbub2_update_dchub()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Damdgpu_dce_stream_encoder.c83 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); in dce110_update_generic_info_packet()
103 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); in dce110_update_generic_info_packet()
108 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in dce110_update_generic_info_packet()
149 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
153 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
157 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
161 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
165 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
169 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
173 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
[all …]
H A Damdgpu_dce_dmcu.c114 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); in dce_get_dmcu_psr_state()
127 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); in dce_get_dmcu_psr_state()
146 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
149 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
153 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_dmcu_set_psr_enable()
196 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
200 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
204 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
208 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
225 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
[all …]
H A Damdgpu_dce_ipp.c56 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); in dce_ipp_cursor_set_position()
60 REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable); in dce_ipp_cursor_set_position()
71 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); in dce_ipp_cursor_set_position()
82 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); in dce_ipp_cursor_set_attributes()
141 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); in dce_ipp_cursor_set_attributes()
151 REG_UPDATE(PRESCALE_GRPH_CONTROL, in dce_ipp_program_prescale()
167 REG_UPDATE(PRESCALE_GRPH_CONTROL, in dce_ipp_program_prescale()
171 REG_UPDATE(INPUT_GAMMA_CONTROL, in dce_ipp_program_prescale()
191 REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); in dce_ipp_program_input_lut()
220 REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); in dce_ipp_program_input_lut()
[all …]
H A Damdgpu_dce_abm.c83 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_abm_set_pipe()
193 REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit); in driver_set_backlight_level()
196 REG_UPDATE(BL_PWM_GRP1_REG_LOCK, in driver_set_backlight_level()
228 REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_pwm_u16_16); in dmcu_set_backlight_level()
236 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET); in dmcu_set_backlight_level()
239 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dmcu_set_backlight_level()
277 REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL, in dce_abm_init()
280 REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL, in dce_abm_init()
283 REG_UPDATE(BL1_PWM_USER_LEVEL, in dce_abm_init()
334 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_abm_set_level()
[all …]
H A Damdgpu_dce_mem_input.c155 REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, in dce_mi_program_pte_vm()
174 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_urgency_watermark()
188 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in dce120_program_urgency_watermark()
207 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_nbp_watermark()
215 REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, in program_nbp_watermark()
220 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_nbp_watermark()
228 REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL, in program_nbp_watermark()
239 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in dce120_program_stutter_watermark()
257 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_stutter_watermark()
261 REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2, in program_stutter_watermark()
[all …]
H A Damdgpu_dce_hwseq.c48 REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst], in dce_enable_fe_clock()
122 REG_UPDATE(BLND_CONTROL[blnd_inst], in dce_set_blender_mode()
137 REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, in dce_disable_sram_shut_down()
145 REG_UPDATE(DCFEV_CLOCK_CONTROL, in dce_underlay_clock_enable()
176 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
186 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
197 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
H A Damdgpu_dce_opp.c180 REG_UPDATE(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
213 REG_UPDATE(FMT_DITHER_RAND_R_SEED, in set_spatial_dither()
216 REG_UPDATE(FMT_DITHER_RAND_G_SEED, in set_spatial_dither()
219 REG_UPDATE(FMT_DITHER_RAND_B_SEED, in set_spatial_dither()
309 REG_UPDATE(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither()
318 REG_UPDATE(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither()
448 REG_UPDATE(FMT_CONTROL, in program_formatter_420_memory()
452 REG_UPDATE(CONTROL, in program_formatter_420_memory()
501 REG_UPDATE(FMT_CONTROL, in program_formatter_reset_dig_resync_fifo()
H A Damdgpu_dce_link_encoder.c148 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); in enable_phy_bypass_mode()
169 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0); in disable_prbs_mode()
238 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete); in set_link_training_complete()
412 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
416 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
426 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
447 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF); in set_dp_phy_pattern_passthrough_mode()
494 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1); in configure_encoder()
525 REG_UPDATE(DP_DPHY_FAST_TRAINING, in dce110_psr_program_dp_dphy_fast_training()
528 REG_UPDATE(DP_DPHY_FAST_TRAINING, in dce110_psr_program_dp_dphy_fast_training()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_stream_encoder.c73 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); in enc1_update_generic_info_packet()
92 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); in enc1_update_generic_info_packet()
96 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in enc1_update_generic_info_packet()
128 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
132 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
136 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
140 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
144 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
148 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
152 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
[all …]
H A Damdgpu_dcn10_opp.c173 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0); in opp1_set_pixel_encoding()
182 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2); in opp1_set_pixel_encoding()
297 REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0); in opp1_program_fmt()
331 REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0); in opp1_program_stereo()
333 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, active_width); in opp1_program_stereo()
341 REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, space2_size); in opp1_program_stereo()
343 REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, space1_size); in opp1_program_stereo()
363 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, oppbuf->active_width); in opp1_program_oppbuf()
371 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, oppbuf->mso_segmentation); in opp1_program_oppbuf()
374 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, oppbuf->mso_overlap_pixel_num); in opp1_program_oppbuf()
[all …]
H A Damdgpu_dcn10_hubp.c79 REG_UPDATE(DCHUBP_CNTL, in hubp1_disconnect()
82 REG_UPDATE(CURSOR_CONTROL, in hubp1_disconnect()
91 REG_UPDATE(DCHUBP_CNTL, in hubp1_disable_control()
112 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); in hubp1_clear_underflow()
120 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); in hubp1_set_hubp_blank_en()
266 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
270 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
275 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
281 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
285 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
[all …]
H A Damdgpu_dcn10_dpp_cm.c361 REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK, in dpp1_cm_configure_regamma_lut()
363 REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK, in dpp1_cm_configure_regamma_lut()
594 REG_UPDATE(CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, 8); in dpp1_enable_cm_block()
595 REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0); in dpp1_enable_cm_block()
608 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0); in dpp1_set_degamma()
611 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1); in dpp1_set_degamma()
614 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2); in dpp1_set_degamma()
617 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3); in dpp1_set_degamma()
635 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3); in dpp1_degamma_ram_select()
637 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4); in dpp1_degamma_ram_select()
[all …]
H A Damdgpu_dcn10_dpp.c285 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3); in dpp1_set_degamma_format_float()
286 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1); in dpp1_set_degamma_format_float()
288 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2); in dpp1_set_degamma_format_float()
289 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0); in dpp1_set_degamma_format_float()
400 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp1_cnv_setup()
421 REG_UPDATE(CURSOR_CONTROL, in dpp1_cnv_setup()
423 REG_UPDATE(CURSOR0_CONTROL, in dpp1_cnv_setup()
441 REG_UPDATE(CURSOR0_COLOR0, in dpp1_set_cursor_attributes()
443 REG_UPDATE(CURSOR0_COLOR1, in dpp1_set_cursor_attributes()
486 REG_UPDATE(CURSOR0_CONTROL, in dpp1_set_cursor_position()
[all …]
H A Ddcn10_dwb.c83 REG_UPDATE(WB_ENABLE, WB_ENABLE, 1); in dwb1_enable()
93 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, 0); in dwb1_disable()
96 REG_UPDATE(WB_ENABLE, WB_ENABLE, 0); in dwb1_disable()
99 REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1); in dwb1_disable()
100 REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0); in dwb1_disable()
H A Damdgpu_dcn10_link_encoder.c120 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); in enable_phy_bypass_mode()
141 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0); in disable_prbs_mode()
210 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete); in set_link_training_complete()
383 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
387 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
397 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
418 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF); in set_dp_phy_pattern_passthrough_mode()
504 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1); in enc1_configure_encoder()
513 REG_UPDATE(DP_DPHY_FAST_TRAINING, in dcn10_psr_program_dp_dphy_fast_training()
516 REG_UPDATE(DP_DPHY_FAST_TRAINING, in dcn10_psr_program_dp_dphy_fast_training()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
H A Damdgpu_hw_gpio.c59 REG_UPDATE(MASK_reg, MASK, gpio->store.mask); in restore_registers()
60 REG_UPDATE(A_reg, A, gpio->store.a); in restore_registers()
61 REG_UPDATE(EN_reg, EN, gpio->store.en); in restore_registers()
112 REG_UPDATE(A_reg, A, value); in dal_hw_gpio_set_value()
119 REG_UPDATE(EN_reg, EN, ~value); in dal_hw_gpio_set_value()
156 REG_UPDATE(EN_reg, EN, 0); in dal_hw_gpio_config_mode()
157 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
162 REG_UPDATE(A_reg, A, 0); in dal_hw_gpio_config_mode()
163 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
168 REG_UPDATE(A_reg, A, 0); in dal_hw_gpio_config_mode()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
H A Damdgpu_dce120_hw_sequencer.c213 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
216 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
219 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()
224 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
227 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
230 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()
235 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
238 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
241 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()

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