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Searched refs:REG_SET (Results 1 – 25 of 53) sorted by relevance

123

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_hubp.c389 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
393 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
398 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
402 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
418 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, in hubp1_program_surface_flip_and_addr()
422 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, in hubp1_program_surface_flip_and_addr()
426 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
430 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
435 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, in hubp1_program_surface_flip_and_addr()
439 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, in hubp1_program_surface_flip_and_addr()
[all …]
H A Damdgpu_dcn10_mpc.c66 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
68 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
70 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
221 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); in mpc1_insert_plane()
225 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_insert_plane()
228 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); in mpc1_insert_plane()
229 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); in mpc1_insert_plane()
243 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id); in mpc1_insert_plane()
309 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, in mpc1_remove_mpcc()
313 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, in mpc1_remove_mpcc()
[all …]
H A Damdgpu_dcn10_dpp_cm.c105 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
159 REG_SET( in program_gamut_remap()
206 REG_SET(CM_TEST_DEBUG_INDEX, 0, in dpp1_cm_program_color_matrix()
240 REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); in dpp1_cm_program_color_matrix()
328 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp1_cm_power_on_regamma_lut()
343 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); in dpp1_cm_program_regamma_lut()
344 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); in dpp1_cm_program_regamma_lut()
345 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg); in dpp1_cm_program_regamma_lut()
347 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); in dpp1_cm_program_regamma_lut()
348 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); in dpp1_cm_program_regamma_lut()
[all …]
H A Damdgpu_dcn10_optc.c84 REG_SET(OTG_VSTARTUP_PARAM, 0, in optc1_program_global_sync()
91 REG_SET(OTG_VREADY_PARAM, 0, in optc1_program_global_sync()
99 REG_SET(OTG_STEREO_CONTROL, 0, in optc1_disable_stereo()
125 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, in optc1_setup_vertical_interrupt1()
135 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, in optc1_setup_vertical_interrupt2()
177 REG_SET(OTG_H_TOTAL, 0, in optc1_program_timing()
208 REG_SET(OTG_V_TOTAL, 0, in optc1_program_timing()
214 REG_SET(OTG_V_TOTAL_MAX, 0, in optc1_program_timing()
216 REG_SET(OTG_V_TOTAL_MIN, 0, in optc1_program_timing()
606 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc1_lock()
[all …]
H A Damdgpu_dcn10_hubbub.c323 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, in hubbub1_program_urgent_watermarks()
346 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, in hubbub1_program_urgent_watermarks()
369 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, in hubbub1_program_urgent_watermarks()
392 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, in hubbub1_program_urgent_watermarks()
428 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, in hubbub1_program_stutter_watermarks()
442 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, in hubbub1_program_stutter_watermarks()
457 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, in hubbub1_program_stutter_watermarks()
471 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, in hubbub1_program_stutter_watermarks()
486 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, in hubbub1_program_stutter_watermarks()
500 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, in hubbub1_program_stutter_watermarks()
[all …]
H A Damdgpu_dcn10_opp.c103 REG_SET(FMT_DITHER_RAND_R_SEED, 0, in opp1_set_spatial_dither()
106 REG_SET(FMT_DITHER_RAND_G_SEED, 0, in opp1_set_spatial_dither()
109 REG_SET(FMT_DITHER_RAND_B_SEED, 0, in opp1_set_spatial_dither()
H A Damdgpu_dcn10_cm_common.c88 REG_SET(reg->start_slope_cntl_b, 0, in cm_helper_program_xfer_func()
90 REG_SET(reg->start_slope_cntl_g, 0, in cm_helper_program_xfer_func()
92 REG_SET(reg->start_slope_cntl_r, 0, in cm_helper_program_xfer_func()
95 REG_SET(reg->start_end_cntl1_b, 0, in cm_helper_program_xfer_func()
101 REG_SET(reg->start_end_cntl1_g, 0, in cm_helper_program_xfer_func()
107 REG_SET(reg->start_end_cntl1_r, 0, in cm_helper_program_xfer_func()
H A Damdgpu_dcn10_dpp_dscl.c588 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in dpp1_dscl_set_manual_ratio_init()
591 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in dpp1_dscl_set_manual_ratio_init()
594 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0, in dpp1_dscl_set_manual_ratio_init()
597 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0, in dpp1_dscl_set_manual_ratio_init()
H A Damdgpu_dcn10_dpp.c130 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in dpp_set_gamut_remap_bypass()
262 REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode); in dpp1_cm_set_regamma_pwl()
398 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp1_cnv_setup()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_vmid.c80 REG_SET(PAGE_TABLE_START_ADDR_HI32, 0, in dcn20_vmid_setup()
82 REG_SET(PAGE_TABLE_START_ADDR_LO32, 0, in dcn20_vmid_setup()
85 REG_SET(PAGE_TABLE_END_ADDR_HI32, 0, in dcn20_vmid_setup()
87 REG_SET(PAGE_TABLE_END_ADDR_LO32, 0, in dcn20_vmid_setup()
94 REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0, in dcn20_vmid_setup()
97 REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0, in dcn20_vmid_setup()
H A Damdgpu_dcn20_hubp.c70 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, in hubp2_set_vm_system_aperture_settings()
73 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, in hubp2_set_vm_system_aperture_settings()
76 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, in hubp2_set_vm_system_aperture_settings()
96 REG_SET(BLANK_OFFSET_1, 0, in hubp2_program_deadline()
99 REG_SET(DST_DIMENSIONS, 0, in hubp2_program_deadline()
106 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, in hubp2_program_deadline()
110 REG_SET(VBLANK_PARAMETERS_1, 0, in hubp2_program_deadline()
114 REG_SET(NOM_PARAMETERS_0, 0, in hubp2_program_deadline()
118 REG_SET(NOM_PARAMETERS_1, 0, in hubp2_program_deadline()
121 REG_SET(NOM_PARAMETERS_4, 0, in hubp2_program_deadline()
[all …]
H A Damdgpu_dcn20_mpc.c71 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); in mpc2_update_blending()
72 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); in mpc2_update_blending()
73 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); in mpc2_update_blending()
148 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
188 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
204 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
247 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
284 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc20_power_on_ogam_lut()
299 REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); in mpc20_configure_ogam_lut()
394 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg); in mpc20_program_ogam_pwl()
[all …]
H A Damdgpu_dcn20_dpp_cm.c104 REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0); in dpp2_program_degamma_lut()
106 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg); in dpp2_program_degamma_lut()
107 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg); in dpp2_program_degamma_lut()
108 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg); in dpp2_program_degamma_lut()
110 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
112 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
114 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
175 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
212 REG_SET( in program_gamut_remap()
257 REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0); in dpp2_program_input_csc()
[all …]
H A Damdgpu_dcn20_optc.c207 REG_SET(OPTC_BYTES_PER_PIXEL, 0, in optc2_set_dsc_config()
235 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_bypass()
267 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_combine()
285 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1); in optc2_set_odm_combine()
329 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc2_triplebuffer_lock()
332 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc2_triplebuffer_lock()
335 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_triplebuffer_lock()
348 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_triplebuffer_unlock()
351 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc2_triplebuffer_unlock()
413 REG_SET(OTG_TRIGA_MANUAL_TRIG, 0, in optc2_program_manual_trigger()
H A Damdgpu_dcn20_hubbub.c378 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, in hubbub2_init_dchub_sys_ctx()
380 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, in hubbub2_init_dchub_sys_ctx()
382 REG_SET(DCN_VM_FB_OFFSET, 0, in hubbub2_init_dchub_sys_ctx()
384 REG_SET(DCN_VM_AGP_BOT, 0, in hubbub2_init_dchub_sys_ctx()
386 REG_SET(DCN_VM_AGP_TOP, 0, in hubbub2_init_dchub_sys_ctx()
388 REG_SET(DCN_VM_AGP_BASE, 0, in hubbub2_init_dchub_sys_ctx()
391 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, in hubbub2_init_dchub_sys_ctx()
393 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, in hubbub2_init_dchub_sys_ctx()
595 REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, in hubbub2_program_watermarks()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Damdgpu_dce_ipp.c134 REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, in dce_ipp_cursor_set_attributes()
137 REG_SET(CUR_SURFACE_ADDRESS, 0, in dce_ipp_cursor_set_attributes()
185 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); in dce_ipp_program_input_lut()
188 REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); in dce_ipp_program_input_lut()
200 REG_SET(DC_LUT_RW_INDEX, 0, in dce_ipp_program_input_lut()
204 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
207 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
210 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
217 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); in dce_ipp_program_input_lut()
H A Damdgpu_dce_transform.c125 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); in setup_scaling_configuration()
149 REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1); in setup_scaling_configuration()
204 REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1); in program_multi_taps_filter()
292 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in program_scl_ratios_inits()
295 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in program_scl_ratios_inits()
363 REG_SET(SCL_VERT_FILTER_CONTROL, 0, in dce_transform_set_scaler()
378 REG_SET(SCL_HORZ_FILTER_CONTROL, 0, in dce_transform_set_scaler()
543 REG_SET(OUT_ROUND_CONTROL, 0, OUT_ROUND_TRUNC_MODE, depth_bits); in set_round()
749 REG_SET(DENORM_CONTROL, 0, DENORM_MODE, denorm_mode); in set_denormalization()
829 REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 1); in program_gamut_remap()
[all …]
H A Damdgpu_dce_mem_input.c418 REG_SET(GRPH_X_START, 0, in program_size_and_rotation()
421 REG_SET(GRPH_Y_START, 0, in program_size_and_rotation()
424 REG_SET(GRPH_X_END, 0, in program_size_and_rotation()
427 REG_SET(GRPH_Y_END, 0, in program_size_and_rotation()
430 REG_SET(GRPH_PITCH, 0, in program_size_and_rotation()
433 REG_SET(HW_ROTATION, 0, in program_size_and_rotation()
599 REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control, in dce_mi_allocate_dmif()
636 REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control, in dce_mi_free_dmif()
658 REG_SET(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0, in program_sec_addr()
672 REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in program_pri_addr()
[all …]
H A Damdgpu_dce_aux.c250 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
254 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
267 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
H A Damdgpu_dcn21_hubbub.c121 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, in hubbub21_init_dchub()
123 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, in hubbub21_init_dchub()
125 REG_SET(DCN_VM_FB_OFFSET, 0, in hubbub21_init_dchub()
127 REG_SET(DCN_VM_AGP_BOT, 0, in hubbub21_init_dchub()
129 REG_SET(DCN_VM_AGP_TOP, 0, in hubbub21_init_dchub()
131 REG_SET(DCN_VM_AGP_BASE, 0, in hubbub21_init_dchub()
178 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, in hubbub21_program_urgent_watermarks()
186 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, in hubbub21_program_urgent_watermarks()
193 REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0, in hubbub21_program_urgent_watermarks()
216 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, in hubbub21_program_urgent_watermarks()
[all …]
H A Damdgpu_dcn21_hubp.c91 REG_SET(VBLANK_PARAMETERS_5, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
98 REG_SET(VBLANK_PARAMETERS_6, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
103 REG_SET(FLIP_PARAMETERS_3, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
108 REG_SET(FLIP_PARAMETERS_4, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
111 REG_SET(FLIP_PARAMETERS_5, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
113 REG_SET(FLIP_PARAMETERS_6, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
344 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, in hubp21_set_vm_system_aperture_settings()
347 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, in hubp21_set_vm_system_aperture_settings()
720 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, in program_surface_flip_and_addr()
724 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, in program_surface_flip_and_addr()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dr300d.h63 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
64 REG_SET(PACKET0_COUNT, (n)))
65 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
67 REG_SET(PACKET3_IT_OPCODE, (op)) | \
68 REG_SET(PACKET3_COUNT, (n)))
H A Drv515d.h203 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
204 REG_SET(PACKET0_COUNT, (n)))
205 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
207 REG_SET(PACKET3_IT_OPCODE, (op)) | \
208 REG_SET(PACKET3_COUNT, (n)))
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
H A Damdgpu_hw_ddc.c124 REG_SET(gpio.MASK_reg, regval, in set_config()
133 REG_SET(gpio.MASK_reg, regval, in set_config()
169 REG_SET(gpio.MASK_reg, regval, in set_config()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
H A Dreg_helper.h47 #ifdef REG_SET
48 #undef REG_SET
65 #define REG_SET(reg_name, initial_val, field, val) \ macro
386 REG_SET(reg, val, f2, v2); }
390 val = REG_SET(reg, val, f2, v2); \
391 REG_SET(reg, val, f3, v3); }

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