| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 159 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID() argument
160 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
294 const TargetRegisterClass *getRegClass(unsigned RCID) const;
|
| H A D | AMDGPUTargetTransformInfo.h | 123 unsigned getNumberOfRegisters(unsigned RCID) const;
|
| H A D | AMDGPUTargetTransformInfo.cpp | 310 unsigned GCNTTIImpl::getNumberOfRegisters(unsigned RCID) const { in getNumberOfRegisters()
312 const TargetRegisterClass *RC = TRI->getRegClass(RCID); in getNumberOfRegisters()
|
| H A D | SIInstrInfo.cpp | 4434 unsigned RCID, in adjustAllocatableRegClass() argument
4439 switch (RCID) { in adjustAllocatableRegClass()
4449 return RCID; in adjustAllocatableRegClass()
4497 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local
4498 RCID = adjustAllocatableRegClass(ST, MRI, Desc, RCID, true); in getOpRegClass()
4499 return RI.getRegClass(RCID); in getOpRegClass()
4507 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove() local
4508 const TargetRegisterClass *RC = RI.getRegClass(RCID); in legalizeOpWithMove()
7379 const auto RCID = MI.getDesc().OpInfo[Idx].RegClass; in isBufferSMRD() local
7380 return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass); in isBufferSMRD()
|
| H A D | SIRegisterInfo.cpp | 2367 SIRegisterInfo::getRegClass(unsigned RCID) const { in getRegClass()
2368 switch ((int)RCID) { in getRegClass()
2377 return AMDGPUGenRegisterInfo::getRegClass(RCID); in getRegClass()
|
| H A D | AMDGPUISelDAGToDAG.cpp | 584 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local
586 Subtarget->getRegisterInfo()->getRegClass(RCID); in getOperandRegClass()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineInstr.cpp | 905 unsigned RCID; in getRegClassConstraint() local
909 InlineAsm::hasRegClassConstraint(Flag, RCID)) in getRegClassConstraint()
910 return TRI->getRegClass(RCID); in getRegClassConstraint()
1748 unsigned RCID = 0; in print() local
1750 InlineAsm::hasRegClassConstraint(Flag, RCID)) { in print()
1752 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in print()
1754 OS << ":RC" << RCID; in print()
|
| H A D | TargetInstrInfo.cpp | 1398 unsigned RCID = 0; in createMIROperandComment() local
1400 InlineAsm::hasRegClassConstraint(Flag, RCID)) { in createMIROperandComment()
1402 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in createMIROperandComment()
1404 OS << ":RC" << RCID; in createMIROperandComment()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 1591 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() argument
1592 switch (RCID) { in getRegBitWidth()
1682 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getRegOperandSize() local
1683 return getRegBitWidth(MRI->getRegClass(RCID)) / 8; in getRegOperandSize()
|
| H A D | AMDGPUBaseInfo.h | 769 unsigned getRegBitWidth(unsigned RCID);
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 249 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods() argument
250 return isRegClass(RCID) || isInlinableImm(type) || isLiteralImm(type); in isRegOrImmWithInputMods()
370 bool isRegClass(unsigned RCID) const;
374 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods() argument
375 return (isRegClass(RCID) || isInlinableImm(type)) && !hasModifiers(); in isRegOrInlineNoMods()
1897 bool AMDGPUOperand::isRegClass(unsigned RCID) const { in isRegClass()
1898 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); in isRegClass()
2453 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg() local
2454 if (RCID == -1) { in getRegularReg()
2460 const MCRegisterClass RC = TRI->getRegClass(RCID); in getRegularReg()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 679 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local
680 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printOperand()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 1532 unsigned RCID; in handleSpecialFP() local
1550 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) { in handleSpecialFP()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 147 unsigned RCID = getRegClassIDForVecVT(ContainerVT); in RISCVTargetLowering() local
149 addRegisterClass(VT, TRI.getRegClass(RCID)); in RISCVTargetLowering()
1133 for (const unsigned RCID : in decomposeSubvectorInsertExtractToSubRegs()
1135 if (VecRegClassID > RCID && SubRegClassID <= RCID) { in decomposeSubvectorInsertExtractToSubRegs()
|