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/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/
H A Da9.s15 R7 = MAX ( R0 , R1 ); define
16 DBGA ( R7.L , 0x0001 );
17 DBGA ( R7.H , 0x0000 );
18 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
19 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
20 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
21 CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
22 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
29 R7 = MAX ( R0 , R1 ); define
30 DBGA ( R7.L , 0x0001 );
[all …]
H A Da10.s16 R7 = MAX ( R0 , R1 ) (V); define
17 DBGA ( R7.L , 0x0001 );
18 DBGA ( R7.H , 0x0002 );
19 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
20 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
21 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
22 CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
23 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
30 R7 = MAX ( R0 , R1 ) (V); define
31 DBGA ( R7.L , 0x0001 );
[all …]
H A Ds13.s15 R7.L = ASHIFT R0.L BY R5.L;
16 DBGA ( R7.L , 0x0010 );
17 DBGA ( R7.H , 0x0000 );
18 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
19 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
20 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
21 CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
22 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
30 R7.L = ASHIFT R0.L BY R5.L;
31 DBGA ( R7.L , 0xf800 );
[all …]
H A Ds14.s16 R7 = 0; define
17 ASTAT = R7;
23 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
24 CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
25 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
26 CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
27 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
32 R7 = 0; define
33 ASTAT = R7;
39 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
[all …]
H A Ds9.s14 R7.L = R0.L << 4;
15 DBGA ( R7.L , 0x0010 );
16 DBGA ( R7.H , 0x0000 );
17 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
18 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
19 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
20 CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
21 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
27 R7.L = R0.L >>> 4;
28 DBGA ( R7.L , 0xf800 );
[all …]
H A Da6.s17 R7 = 0; define
18 ASTAT = R7;
19 R7 = R0 +|+ R1; define
20 DBGA ( R7.L , 0x8000 );
21 DBGA ( R7.H , 0x0020 );
22 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
23 CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
24 CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
25 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
32 R7 = 0; define
[all …]
H A Ds18.s14 R7 = 0; define
15 ASTAT = R7;
21 CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
22 CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
23 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
24 CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
25 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
29 R7 = 0; define
30 ASTAT = R7;
36 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
[all …]
H A Dm2.s24 R7 = 0; define
25 ASTAT = R7;
31 R7.L = A1.x;
35 DBGA ( R7.L , 0x0000 );
36 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
37 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
38 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
39 CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
40 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
43 R7 = 0; define
[all …]
H A Ds19.s14 R7 = 0; define
15 ASTAT = R7;
22 CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
23 CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
24 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
25 CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
26 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
30 R7 = 0; define
31 ASTAT = R7;
38 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
[all …]
H A Ds15.s13 R7 = EXTRACT( R0, R1.L ) (Z); define
14 DBGA ( R7.L , 0x34de );
15 DBGA ( R7.H , 0 );
20 R7 = EXTRACT( R0, R1.L ) (Z); define
21 DBGA ( R7.L , 0x34de );
22 DBGA ( R7.H , 0x0002 );
27 R7 = EXTRACT( R0, R1.L ) (Z); define
28 DBGA ( R7.L , 0 );
29 DBGA ( R7.H , 0 );
34 R7 = EXTRACT( R0, R1.L ) (Z); define
[all …]
H A Ddsp_a7.s18 R7 = 0; define
19 ASTAT = R7;
20 R7 = R0 +|- R1; define
21 DBGA ( R7.L , 0x0000 );
22 DBGA ( R7.H , 0x0020 );
23 CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
24 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
25 CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
26 CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
33 R7 = 0; define
[all …]
H A Ddsp_a4.s17 R7 = 0; define
18 ASTAT = R7;
22 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
23 CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
24 CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
25 CC = VS; R7 = CC; DBGA ( R7.L , 0x1 );
26 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
31 R7 = 0; define
32 ASTAT = R7;
36 CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
[all …]
H A Ds16.s14 R7 = DEPOSIT( R0, R1 ); define
15 DBGA ( R7.L , 0xfead );
16 DBGA ( R7.H , 0x123f );
22 R7 = DEPOSIT( R0, R1 ); define
23 DBGA ( R7.L , 0xfead );
24 DBGA ( R7.H , 0x1234 );
30 R7 = DEPOSIT( R0, R1 ); define
31 DBGA ( R7.L , 0xfead );
32 DBGA ( R7.H , 0x1235 );
38 R7 = DEPOSIT( R0, R1 ); define
[all …]
H A Ds4.s31 R7 = 0; define
32 ASTAT = R7;
36 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
37 CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
38 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
39 CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
40 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
48 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
49 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
50 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
[all …]
H A Dc_cc2stat_cc_an.s20 R7 = 0x00; define
21 ASTAT = R7; // cc = 0, AN = 0
25 R7 = 0x02; define
26 ASTAT = R7; // cc = 0, AN = 1
30 R7 = 0x20; define
31 ASTAT = R7; // cc = 1, AN = 0
35 R7 = 0x22; define
36 ASTAT = R7; // cc = 1, AN = 1
41 R7 = 0x00; define
42 ASTAT = R7; // cc = 0, AN = 0
[all …]
H A Dc_cc2stat_cc_az.s20 R7 = 0x00; define
21 ASTAT = R7; // cc = 0, AZ = 0
25 R7 = 0x01; define
26 ASTAT = R7; // cc = 0, AZ = 1
30 R7 = 0x20; define
31 ASTAT = R7; // cc = 1, AZ = 0
35 R7 = 0x21; define
36 ASTAT = R7; // cc = 1, AZ = 1
41 R7 = 0x00; define
42 ASTAT = R7; // cc = 0, AZ = 0
[all …]
H A Da5.s20 R7 = 0; define
21 ASTAT = R7;
25 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
26 CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
27 CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
28 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
36 R7 = 0; define
37 ASTAT = R7;
41 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
42 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
[all …]
H A Dc_cc2stat_cc_aq.s20 R7 = 0x00; define
21 ASTAT = R7; // cc = 0, AQ = 0
25 R7 = 0x40 (X); define
26 ASTAT = R7; // cc = 0, AQ = 1
30 R7 = 0x20; define
31 ASTAT = R7; // cc = 1, AQ = 0
35 R7 = 0x60 (X); define
36 ASTAT = R7; // cc = 1, AQ = 1
41 R7 = 0x00; define
42 ASTAT = R7; // cc = 0, AQ = 0
[all …]
H A Ddsp_a8.s17 R7 = 0; define
18 ASTAT = R7;
19 R6 = R0 + R1, R7 = R0 - R1 (NS);
22 DBGA ( R7.L , 0xfffe );
23 DBGA ( R7.H , 0x7fff );
24 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
25 CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
26 CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
27 CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
34 R7 = 0; define
[all …]
H A Dc_cc2stat_cc_av0.S20 R7 = 0x00; define
21 ASTAT = R7; // cc = 0, AV0 = 0
25 imm32 R7, _AV0;
26 ASTAT = R7; // cc = 0, AV0 = 1
30 imm32 R7, _CC;
31 ASTAT = R7; // cc = 1, AV0 = 0
35 imm32 R7, (_CC|_AV0);
36 ASTAT = R7; // cc = 1, AV0 = 1
41 R7 = 0x00; define
42 ASTAT = R7; // cc = 0, AV0 = 0
[all …]
H A Dc_cc2stat_cc_av1.S19 R7 = 0x00; define
20 ASTAT = R7; // cc = 0, AV1 = 0
24 imm32 R7, _AV1;
25 ASTAT = R7; // cc = 0, AV1 = 1
29 imm32 R7, _CC;
30 ASTAT = R7; // cc = 1, AV1 = 0
34 imm32 R7, (_CC|_AV1);
35 ASTAT = R7; // cc = 1, AV1 = 1
40 R7 = 0x00; define
41 ASTAT = R7; // cc = 0, AV1 = 0
[all …]
H A Dc_cc2stat_cc_ac.S19 imm32 R7, 0x00;
20 ASTAT = R7; // cc = 0, AC0 = 0
24 imm32 R7, _AC0;
25 ASTAT = R7; // cc = 0, AC0 = 1
29 imm32 R7, _CC;
30 ASTAT = R7; // cc = 1, AC0 = 0
34 imm32 R7, (_CC|_AC0);
35 ASTAT = R7; // cc = 1, AC0 = 1
40 imm32 R7, 0x00;
41 ASTAT = R7; // cc = 0, AC0 = 0
[all …]
H A Ds5.s14 R7 = 0; define
15 CC = R7;
20 R7 = CC; define
21 DBGA ( R7.L , 0x0001 );
26 R7 = 0; define
27 CC = R7;
33 R7 = CC; define
34 DBGA ( R7.L , 0x0001 );
39 R7 = 0; define
40 CC = R7;
[all …]
H A Ddsp_d1.s15 R7 = I0; define
16 R1 = R7 - R2
19 R7 = I0; define
21 R1 = R7 - R2;
24 R7 = I0; define
25 R1 = R7 - R2
34 R7 = I0; define
35 R1 = R7 - R2
38 R7 = I0; define
39 R1 = R7 - R2
[all …]
H A Da11.S9 R7 = 0; define
10 ASTAT = R7;
17 R7.L = R0 (RND);
19 CHECKREG R7, 0x7fff;
27 R7.H = R0 (RND);
29 CHECKREG R7, 0x7fff7fff;
37 R7.L = R0 (RND);
39 CHECKREG R7, 0x7fff7ff1
50 R7.H = R0 (RND);
52 CHECKREG R7, 0x7ff17ff1
[all …]

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