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Searched refs:ProcResource (Results 1 – 25 of 53) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/
H A DResourcePressureView.cpp29 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in ResourcePressureView() local
30 unsigned NumUnits = ProcResource.NumUnits; in ResourcePressureView()
32 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in ResourcePressureView()
36 R2VIndex += ProcResource.NumUnits; in ResourcePressureView()
73 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printColumnNames() local
74 unsigned NumUnits = ProcResource.NumUnits; in printColumnNames()
76 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in printColumnNames()
112 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printResourcePressurePerIter() local
113 unsigned NumUnits = ProcResource.NumUnits; in printResourcePressurePerIter()
115 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in printResourcePressurePerIter()
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H A DSchedulerStatistics.cpp141 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printSchedulerUsage() local
142 if (ProcResource.BufferSize <= 0) in printSchedulerUsage()
147 double AlmostFullThreshold = (double)(ProcResource.BufferSize * 4) / 5; in printSchedulerUsage()
151 FOS << ProcResource.Name; in printSchedulerUsage()
160 BU.MaxUsedSlots == static_cast<unsigned>(ProcResource.BufferSize)) in printSchedulerUsage()
166 FOS << ProcResource.BufferSize << '\n'; in printSchedulerUsage()
H A DInstructionView.cpp42 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in toJSON() local
43 unsigned NumUnits = ProcResource.NumUnits; in toJSON()
45 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in toJSON()
49 ResNameStream << ProcResource.Name; in toJSON()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td37 def FalkorUnitB : ProcResource<1>; // Branch
38 def FalkorUnitLD : ProcResource<1>; // Load pipe
39 def FalkorUnitSD : ProcResource<1>; // Store data
40 def FalkorUnitST : ProcResource<1>; // Store pipe
41 def FalkorUnitX : ProcResource<1>; // Complex arithmetic
42 def FalkorUnitY : ProcResource<1>; // Simple arithmetic
43 def FalkorUnitZ : ProcResource<1>; // Simple arithmetic
45 def FalkorUnitVSD : ProcResource<1>; // Vector store data
46 def FalkorUnitVX : ProcResource<1>; // Vector X-pipe
47 def FalkorUnitVY : ProcResource<1>; // Vector Y-pipe
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H A DAArch64SchedExynosM5.td36 def M5UnitA : ProcResource<2>; // Simple integer
37 def M5UnitC : ProcResource<2>; // Simple and complex integer
39 def M5UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
40 def M5UnitE : ProcResource<2>; // Simple 32-bit integer
42 def M5UnitF : ProcResource<2>; // CRC (inside C)
43 def M5UnitB : ProcResource<1>; // Branch
44 def M5UnitL0 : ProcResource<1>; // Load
45 def M5UnitS0 : ProcResource<1>; // Store
46 def M5PipeLS : ProcResource<1>; // Load/Store
48 def M5UnitL1 : ProcResource<1>;
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H A DAArch64SchedExynosM3.td37 def M3UnitA : ProcResource<2>; // Simple integer
38 def M3UnitC : ProcResource<2>; // Simple and complex integer
39 def M3UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
40 def M3UnitB : ProcResource<2>; // Branch
41 def M3UnitL : ProcResource<2>; // Load
42 def M3UnitS : ProcResource<1>; // Store
43 def M3PipeF0 : ProcResource<1>; // FP #0
45 def M3UnitFMAC0 : ProcResource<1>; // FP multiplication
46 def M3UnitFADD0 : ProcResource<1>; // Simple FP
47 def M3UnitFCVT0 : ProcResource<1>; // FP conversion
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H A DAArch64SchedExynosM4.td36 def M4UnitA : ProcResource<2>; // Simple integer
37 def M4UnitC : ProcResource<2>; // Simple and complex integer
39 def M4UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
41 def M4UnitE : ProcResource<1>; // CRC (inside C0)
42 def M4UnitB : ProcResource<2>; // Branch
43 def M4UnitL0 : ProcResource<1>; // Load
44 def M4UnitS0 : ProcResource<1>; // Store
45 def M4PipeLS : ProcResource<1>; // Load/Store
47 def M4UnitL1 : ProcResource<1>;
48 def M4UnitS1 : ProcResource<1>;
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H A DAArch64SchedKryo.td40 def KryoUnitXA : ProcResource<1>; // Type X(A) micro-ops
41 def KryoUnitXB : ProcResource<1>; // Type X(B) micro-ops
42 def KryoUnitYA : ProcResource<1>; // Type Y(A) micro-ops
43 def KryoUnitYB : ProcResource<1>; // Type Y(B) micro-ops
52 def KryoUnitLSA : ProcResource<1>; // Type LS(A) micro-ops
53 def KryoUnitLSB : ProcResource<1>; // Type LS(B) micro-ops
H A DAArch64SchedA55.td38 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since the
41 def CortexA55UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
42 def CortexA55UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC, 64-bi wide
43 def CortexA55UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division, not pipelined
44 def CortexA55UnitLd : ProcResource<1> { let BufferSize = 0; } // Load pipe
45 def CortexA55UnitSt : ProcResource<1> { let BufferSize = 0; } // Store pipe
46 def CortexA55UnitB : ProcResource<1> { let BufferSize = 0; } // Branch
51 def CortexA55UnitFPALU : ProcResource<2> { let BufferSize = 0; } // FP ALU
52 def CortexA55UnitFPMAC : ProcResource<2> { let BufferSize = 0; } // FP MAC
53 def CortexA55UnitFPDIV : ProcResource<1> { let BufferSize = 0; } // FP Div/SQRT, 64/128
H A DAArch64SchedA53.td37 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
40 def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
41 def A53UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
42 def A53UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division
43 def A53UnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store
44 def A53UnitB : ProcResource<1> { let BufferSize = 0; } // Branch
45 def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
46 def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
H A DAArch64SchedThunderX.td35 def THXT8XUnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
36 def THXT8XUnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
37 def THXT8XUnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division
38 def THXT8XUnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store
39 def THXT8XUnitBr : ProcResource<1> { let BufferSize = 0; } // Branch
40 def THXT8XUnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
41 def THXT8XUnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mul/Div/Sqrt
H A DAArch64SchedCyclone.td29 def CyUnitI : ProcResource<4> {
34 def CyUnitB : ProcResource<2> {
40 def CyUnitBR : ProcResource<1> {
46 def CyUnitIS : ProcResource<2> {
52 def CyUnitIM : ProcResource<1> {
58 def CyUnitID : ProcResource<1> {
65 def CyUnitIntDiv : ProcResource<1>;
68 def CyUnitLS : ProcResource<2> {
73 def CyUnitV : ProcResource<3> {
77 def CyUnitVM : ProcResource<2> {
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCScheduleP9.td57 def DISPx02 : ProcResource<2>;
58 def DISPx13 : ProcResource<2>;
61 def DISPxab : ProcResource<2>;
63 def DISPb01 : ProcResource<2>;
77 def IP_AGEN : ProcResource<4>;
78 def IP_EXEC : ProcResource<4>;
79 def IP_EXECE : ProcResource<2> {
83 def IP_EXECO : ProcResource<2> {
90 def ALU : ProcResource<4>;
91 def ALUE : ProcResource<2> {
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
H A DInstructionTables.cpp34 const MCProcResourceDesc &ProcResource = *SM.getProcResource(Index); in execute() local
35 unsigned NumUnits = ProcResource.NumUnits; in execute()
36 if (!ProcResource.SubUnitsIdxBegin) { in execute()
50 unsigned SubUnitIdx = ProcResource.SubUnitsIdxBegin[I1]; in execute()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVSchedRocket.td25 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
29 def RocketUnitALU : ProcResource<1>; // Int ALU
30 def RocketUnitIMul : ProcResource<1>; // Int Multiply
31 def RocketUnitMem : ProcResource<1>; // Load/Store
32 def RocketUnitB : ProcResource<1>; // Branch
34 def RocketUnitFPALU : ProcResource<1>; // FP ALU
38 def RocketUnitIDiv : ProcResource<1>; // Int Division
39 def RocketUnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt
H A DRISCVSchedSiFive7.td27 def SiFive7PipeA : ProcResource<1>;
28 def SiFive7PipeB : ProcResource<1>;
32 def SiFive7IDiv : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
33 def SiFive7FDiv : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSISchedule.td92 def HWBranch : ProcResource<1> {
95 def HWExport : ProcResource<1> {
98 def HWLGKM : ProcResource<1> {
101 def HWSALU : ProcResource<1> {
104 def HWVMEM : ProcResource<1> {
107 def HWVALU : ProcResource<1> {
110 def HWTransVALU : ProcResource<1> { // Transcendental VALU
113 def HWRC : ProcResource<1> { // Register destination cache
116 def HWXDL : ProcResource<1> { // MFMA CU
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetPfmCounters.td21 // Issue counters can be tied to a ProcResource
24 // The name of the ProcResource on which uops are issued. This is used by
27 // ProcResource.
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMScheduleM7.td38 def M7UnitLoadL : ProcResource<1> { let BufferSize = 0; }
39 def M7UnitLoadH : ProcResource<1> { let BufferSize = 0; }
41 def M7UnitStore : ProcResource<1> { let BufferSize = 0; }
42 def M7UnitALU : ProcResource<2>;
43 def M7UnitShift1 : ProcResource<1> { let BufferSize = 0; }
44 def M7UnitShift2 : ProcResource<1> { let BufferSize = 0; }
45 def M7UnitMAC : ProcResource<1> { let BufferSize = 0; }
46 def M7UnitBranch : ProcResource<1> { let BufferSize = 0; }
47 def M7UnitVFP : ProcResource<1> { let BufferSize = 0; }
48 def M7UnitVPortL : ProcResource<1> { let BufferSize = 0; }
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td32 def P5600ALQ : ProcResource<1> { let BufferSize = 16; }
33 def P5600IssueALU : ProcResource<1> { let Super = P5600ALQ; }
47 def P5600AGQ : ProcResource<3> { let BufferSize = 16; }
48 def P5600IssueAL2 : ProcResource<1> { let Super = P5600AGQ; }
49 def P5600IssueCTISTD : ProcResource<1> { let Super = P5600AGQ; }
50 def P5600IssueLDST : ProcResource<1> { let Super = P5600AGQ; }
52 def P5600AL2Div : ProcResource<1>;
54 def P5600CTISTD : ProcResource<1>;
231 def P5600FPQ : ProcResource<3> { let BufferSize = 16; }
232 def P5600IssueFPUS : ProcResource<1> { let Super = P5600FPQ; }
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H A DMipsScheduleGeneric.td39 def GenericALU : ProcResource<1> { let BufferSize = 1; }
40 def GenericIssueALU : ProcResource<1> { let Super = GenericALU; }
139 def GenericMDU : ProcResource<1> { let BufferSize = 1; }
140 def GenericIssueMDU : ProcResource<1> { let Super = GenericALU; }
141 def GenericIssueDIV : ProcResource<1> { let Super = GenericMDU; }
274 def GenericIssueCTISTD : ProcResource<1> { let Super = GenericALU; }
276 def GenericLDST : ProcResource<1> { let BufferSize = 1; }
277 def GenericIssueLDST : ProcResource<1> { let Super = GenericLDST; }
434 def GenericCOP0 : ProcResource<1> { let BufferSize = 1; }
436 def GenericIssueCOP0 : ProcResource<1> { let Super = GenericCOP0; }
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ScheduleBdVer2.td50 def PdEX0 : ProcResource<1>; // ALU, Integer Pipe0
51 def PdEX1 : ProcResource<1>; // ALU, Integer Pipe1
55 def PdAGLU01 : ProcResource<2>; // AGU, Integer Pipe[23]
63 def PdFPU0 : ProcResource<1>; // Vector/FPU Pipe0
64 def PdFPU1 : ProcResource<1>; // Vector/FPU Pipe1
65 def PdFPU2 : ProcResource<1>; // Vector/FPU Pipe2
66 def PdFPU3 : ProcResource<1>; // Vector/FPU Pipe3
133 def PdLoad : ProcResource<2> {
141 def PdStore : ProcResource<1> {
152 def PdDiv : ProcResource<1>; // PdEX0; unpipelined integer division
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H A DX86ScheduleSLM.td34 def SLM_IEC_RSV0 : ProcResource<1>;
35 def SLM_IEC_RSV1 : ProcResource<1>;
36 def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
37 def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }
38 def SLM_MEC_RSV : ProcResource<1>;
44 def SLMDivider : ProcResource<1>;
45 def SLMFPMultiplier : ProcResource<1>;
46 def SLMFPDivider : ProcResource<1>;
H A DX86ScheduleBtVer2.td33 def JALU0 : ProcResource<1>; // Integer Pipe0: integer ALU0 (also handle FP->INT jam)
34 def JALU1 : ProcResource<1>; // Integer Pipe1: integer ALU1/MUL/DIV
35 def JLAGU : ProcResource<1>; // Integer Pipe2: LAGU
36 def JSAGU : ProcResource<1>; // Integer Pipe3: SAGU (also handles 3-operand LEA)
37 def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA
38 def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM
88 def JDiv : ProcResource<1>; // integer division
89 def JMul : ProcResource<1>; // integer multiplication
90 def JVALU0 : ProcResource<1>; // vector integer
91 def JVALU1 : ProcResource<1>; // vector integer
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td54 def ALU : ProcResource<1> { let BufferSize = 0; }
55 def LdSt : ProcResource<1> { let BufferSize = 0; }

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