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Searched refs:PredCost (Results 1 – 12 of 12) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h210 unsigned *PredCost = nullptr) const override;
H A DR600InstrInfo.cpp989 unsigned *PredCost) const { in getInstrLatency()
990 if (PredCost) in getInstrLatency()
991 *PredCost = 2; in getInstrLatency()
H A DSIInstrInfo.h1112 unsigned *PredCost = nullptr) const override;
H A DSIInstrInfo.cpp7820 unsigned *PredCost) const { in getInstrLatency()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h280 unsigned *PredCost = nullptr) const override;
H A DHexagonInstrInfo.cpp1884 unsigned *PredCost) const { in getInstrLatency()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h313 unsigned *PredCost = nullptr) const override;
H A DPPCInstrInfo.cpp138 unsigned *PredCost) const { in getInstrLatency()
140 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost); in getInstrLatency()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp2131 unsigned PredCost = (TCycles + FCycles + TExtra + FExtra) * ScalingUpFactor; in isProfitableToIfCvt() local
2149 PredCost -= 1 * ScalingUpFactor; in isProfitableToIfCvt()
2158 PredCost += ((TCycles + FCycles - 4) / 4) * ScalingUpFactor; in isProfitableToIfCvt()
2169 return PredCost <= UnpredCost; in isProfitableToIfCvt()
4706 unsigned *PredCost) const { in getInstrLatency()
4719 Latency += getInstrLatency(ItinData, *I, PredCost); in getInstrLatency()
4725 if (PredCost && (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) && in getInstrLatency()
4729 *PredCost = 1; in getInstrLatency()
H A DARMBaseInstrInfo.h454 unsigned *PredCost = nullptr) const override;
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1603 unsigned *PredCost = nullptr) const;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp1153 unsigned *PredCost) const { in getInstrLatency()