Searched refs:PLL1 (Results 1 – 4 of 4) sorted by relevance
128 #define PLL1 117 macro
185 #define PLL1 176 macro
196 * that is parent of TIMCLK, PLL1 and PLL2218 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
445 * Put high-speed peripherals under PLL1, such that we can change the