Searched refs:PHY_CLK_RST_MPLL_MULT_24M (Results 1 – 1 of 1) sorted by relevance
56 #define PHY_CLK_RST_MPLL_MULT_24M 0x68 macro210 val |= __SHIFTIN(PHY_CLK_RST_MPLL_MULT_24M, PHY_CLK_RST_MPLL_MULT); in exynos_usbdrdphy_init()