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Searched refs:PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT (Results 1 – 2 of 2) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h4495 #define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x00000000 macro
H A Dbif_4_1_sh_mask.h9568 #define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x0 macro