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/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/
H A Dl0.s7 loadsym P0, tab;
8 R0 = [ P0 ++ ];
9 R1 = [ P0 ++ ];
10 R2 = [ P0 ++ ];
11 R3 = [ P0 ++ ];
12 R4 = [ P0 ++ ];
13 R5 = [ P0 ++ ];
14 R6 = [ P0 ++ ];
15 R7 = [ P0 ++ ];
26 loadsym P0, tab2;
[all …]
H A Dc_progctrl_csync_mmr.S56 [ P0 ++ ] = R0;
59 [ P0 ++ ] = R0;
62 [ P0 ++ ] = R0;
65 [ P0 ++ ] = R0;
67 [ P0 ++ ] = R0; // IVT4 not used
70 [ P0 ++ ] = R0;
73 [ P0 ++ ] = R0;
76 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0;
82 [ P0 ++ ] = R0;
[all …]
H A Dc_mmr_loop.S50 [ P0 ++ ] = R0;
53 [ P0 ++ ] = R0;
56 [ P0 ++ ] = R0;
59 [ P0 ++ ] = R0;
61 [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4)
64 [ P0 ++ ] = R0;
67 [ P0 ++ ] = R0;
70 [ P0 ++ ] = R0;
73 [ P0 ++ ] = R0;
76 [ P0 ++ ] = R0;
[all …]
H A Dse_loop_mv2lc.S68 [ P0 ++ ] = R0;
70 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0;
74 [ P0 ++ ] = R0;
75 [ P0 ++ ] = R0; // IVT4 not used
77 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0;
81 [ P0 ++ ] = R0;
83 [ P0 ++ ] = R0;
85 [ P0 ++ ] = R0;
[all …]
H A Dc_mmr_timer.S50 [ P0 ++ ] = R0;
53 [ P0 ++ ] = R0;
56 [ P0 ++ ] = R0;
59 [ P0 ++ ] = R0;
61 [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4)
64 [ P0 ++ ] = R0;
67 [ P0 ++ ] = R0;
69 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0;
75 [ P0 ++ ] = R0;
[all …]
H A Dse_loop_ppm.S68 [ P0 ++ ] = R0;
70 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0;
74 [ P0 ++ ] = R0;
75 [ P0 ++ ] = R0; // IVT4 not used
77 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0;
81 [ P0 ++ ] = R0;
83 [ P0 ++ ] = R0;
85 [ P0 ++ ] = R0;
[all …]
H A Dse_loop_ppm_1.S68 [ P0 ++ ] = R0;
70 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0;
74 [ P0 ++ ] = R0;
75 [ P0 ++ ] = R0; // IVT4 not used
77 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0;
81 [ P0 ++ ] = R0;
83 [ P0 ++ ] = R0;
85 [ P0 ++ ] = R0;
[all …]
H A Dse_oneins_zoff.S84 [ P0 ++ ] = R0;
86 [ P0 ++ ] = R0;
88 [ P0 ++ ] = R0;
90 [ P0 ++ ] = R0;
91 [ P0 ++ ] = R0; // IVT4 not used
93 [ P0 ++ ] = R0;
95 [ P0 ++ ] = R0;
97 [ P0 ++ ] = R0;
99 [ P0 ++ ] = R0;
101 [ P0 ++ ] = R0;
[all …]
H A Dse_loop_nest_ppm_2.S68 [ P0 ++ ] = R0;
70 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0;
74 [ P0 ++ ] = R0;
75 [ P0 ++ ] = R0; // IVT4 not used
77 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0;
81 [ P0 ++ ] = R0;
83 [ P0 ++ ] = R0;
85 [ P0 ++ ] = R0;
[all …]
H A Dlmu_excpt_prot1.S34 [ P0 ++ ] = R0; // 0
35 [ P0 ++ ] = R0; // 1
36 [ P0 ++ ] = R0; // 2
37 [ P0 ++ ] = R0; // 3
38 [ P0 ++ ] = R0; // 4
39 [ P0 ++ ] = R0; // 5
40 [ P0 ++ ] = R0; // 6
41 [ P0 ++ ] = R0; // 7
42 [ P0 ++ ] = R0; // 8
43 [ P0 ++ ] = R0; // 9
[all …]
H A Dlmu_excpt_prot0.S32 [ P0 ++ ] = R0; // 0
33 [ P0 ++ ] = R0; // 1
34 [ P0 ++ ] = R0; // 2
35 [ P0 ++ ] = R0; // 3
36 [ P0 ++ ] = R0; // 4
37 [ P0 ++ ] = R0; // 5
38 [ P0 ++ ] = R0; // 6
39 [ P0 ++ ] = R0; // 7
40 [ P0 ++ ] = R0; // 8
41 [ P0 ++ ] = R0; // 9
[all …]
H A Da0shift.S42 P0 = ASTAT; define
43 CHECKREG P0, (_VS|_V|_V_COPY);
54 P0 = ASTAT; define
55 CHECKREG P0, (_VS|_V|_V_COPY);
59 P0 = ASTAT; define
60 CHECKREG P0, (_VS|_V|_V_COPY|_AN);
62 P0 = ASTAT; define
63 CHECKREG P0, (_VS|_V|_V_COPY|_AN);
66 P0 = ASTAT; define
67 CHECKREG P0, (_VS|_AN);
[all …]
H A Dse_stall_if2.S84 [ P0 ++ ] = R0;
86 [ P0 ++ ] = R0;
88 [ P0 ++ ] = R0;
90 [ P0 ++ ] = R0;
91 [ P0 ++ ] = R0; // IVT4 not used
93 [ P0 ++ ] = R0;
95 [ P0 ++ ] = R0;
97 [ P0 ++ ] = R0;
99 [ P0 ++ ] = R0;
101 [ P0 ++ ] = R0;
[all …]
H A Dc_interr_timer_tcount.S66 [ P0 ++ ] = R0;
69 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0;
75 [ P0 ++ ] = R0;
77 [ P0 ++ ] = R0; // IVT4 not used
80 [ P0 ++ ] = R0;
83 [ P0 ++ ] = R0;
86 [ P0 ++ ] = R0;
89 [ P0 ++ ] = R0;
92 [ P0 ++ ] = R0;
[all …]
H A Dse_loop_nest_ppm_1.S68 [ P0 ++ ] = R0;
70 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0;
74 [ P0 ++ ] = R0;
75 [ P0 ++ ] = R0; // IVT4 not used
77 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0;
81 [ P0 ++ ] = R0;
83 [ P0 ++ ] = R0;
85 [ P0 ++ ] = R0;
[all …]
H A Dse_loop_nest_ppm.S68 [ P0 ++ ] = R0;
70 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0;
74 [ P0 ++ ] = R0;
75 [ P0 ++ ] = R0; // IVT4 not used
77 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0;
81 [ P0 ++ ] = R0;
83 [ P0 ++ ] = R0;
85 [ P0 ++ ] = R0;
[all …]
H A Dse_loop_ppm_int.S68 [ P0 ++ ] = R0;
70 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0;
74 [ P0 ++ ] = R0;
75 [ P0 ++ ] = R0; // IVT4 not used
77 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0;
81 [ P0 ++ ] = R0;
83 [ P0 ++ ] = R0;
85 [ P0 ++ ] = R0;
[all …]
H A Ddbg_jmp_src_kill.S72 [ P0 ++ ] = R0;
74 [ P0 ++ ] = R0;
76 [ P0 ++ ] = R0;
78 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0; // IVT4 not used
81 [ P0 ++ ] = R0;
83 [ P0 ++ ] = R0;
85 [ P0 ++ ] = R0;
87 [ P0 ++ ] = R0;
89 [ P0 ++ ] = R0;
[all …]
H A Dse_loop_lr.S68 [ P0 ++ ] = R0;
70 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0;
74 [ P0 ++ ] = R0;
75 [ P0 ++ ] = R0; // IVT4 not used
77 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0;
81 [ P0 ++ ] = R0;
83 [ P0 ++ ] = R0;
85 [ P0 ++ ] = R0;
[all …]
H A Dc_progctrl_excpt.S55 [ P0 ++ ] = R0;
58 [ P0 ++ ] = R0;
61 [ P0 ++ ] = R0;
64 [ P0 ++ ] = R0;
66 [ P0 ++ ] = R0; // IVT4 not used
69 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0;
75 [ P0 ++ ] = R0;
78 [ P0 ++ ] = R0;
81 [ P0 ++ ] = R0;
[all …]
H A Dse_brtarget_stall.S84 [ P0 ++ ] = R0;
86 [ P0 ++ ] = R0;
88 [ P0 ++ ] = R0;
90 [ P0 ++ ] = R0;
91 [ P0 ++ ] = R0; // IVT4 not used
93 [ P0 ++ ] = R0;
95 [ P0 ++ ] = R0;
97 [ P0 ++ ] = R0;
99 [ P0 ++ ] = R0;
101 [ P0 ++ ] = R0;
[all …]
H A Ddbg_brtkn_nprd_src_kill.S73 [ P0 ++ ] = R0;
75 [ P0 ++ ] = R0;
77 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0;
80 [ P0 ++ ] = R0; // IVT4 not used
82 [ P0 ++ ] = R0;
84 [ P0 ++ ] = R0;
86 [ P0 ++ ] = R0;
88 [ P0 ++ ] = R0;
90 [ P0 ++ ] = R0;
[all …]
H A Ddbg_brprd_ntkn_src_kill.S74 [ P0 ++ ] = R0;
76 [ P0 ++ ] = R0;
78 [ P0 ++ ] = R0;
80 [ P0 ++ ] = R0;
81 [ P0 ++ ] = R0; // IVT4 not used
83 [ P0 ++ ] = R0;
85 [ P0 ++ ] = R0;
87 [ P0 ++ ] = R0;
89 [ P0 ++ ] = R0;
91 [ P0 ++ ] = R0;
[all …]
H A Dse_misaligned_fetch.S62 [ P0 ++ ] = R0;
65 [ P0 ++ ] = R0;
68 [ P0 ++ ] = R0;
71 [ P0 ++ ] = R0;
73 [ P0 ++ ] = R0; // IVT4 not used
76 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0;
82 [ P0 ++ ] = R0;
85 [ P0 ++ ] = R0;
88 [ P0 ++ ] = R0;
[all …]
H A Dc_except_sys_sstep.S56 [ P0 ++ ] = R0;
59 [ P0 ++ ] = R0;
62 [ P0 ++ ] = R0;
65 [ P0 ++ ] = R0;
67 [ P0 ++ ] = R0; // IVT4 not used
70 [ P0 ++ ] = R0;
73 [ P0 ++ ] = R0;
76 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0;
82 [ P0 ++ ] = R0;
[all …]

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