/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.h | 59 static BranchPredicate getBranchPredicate(unsigned Opcode); 92 unsigned Opcode) const; 96 unsigned Opcode) const; 99 MachineInstr &Inst, unsigned Opcode, 106 unsigned Opcode, 343 bool isSALU(uint16_t Opcode) const { in isSALU() argument 344 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU() 351 bool isVALU(uint16_t Opcode) const { in isVALU() argument 352 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU() 359 bool isVMEM(uint16_t Opcode) const { in isVMEM() argument [all …]
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H A D | R600InstrInfo.h | 85 bool isALUInstr(unsigned Opcode) const; 86 bool hasInstrModifiers(unsigned Opcode) const; 87 bool isLDSInstr(unsigned Opcode) const; 88 bool isLDSRetInstr(unsigned Opcode) const; 94 bool isTransOnly(unsigned Opcode) const; 96 bool isVectorOnly(unsigned Opcode) const; 98 bool isExport(unsigned Opcode) const; 100 bool usesVertexCache(unsigned Opcode) const; 102 bool usesTextureCache(unsigned Opcode) const; 105 bool mustBeLastInClause(unsigned Opcode) const; [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
H A D | BPFMISimplifyPatchable.cpp | 71 unsigned Opcode); 109 unsigned Opcode = DefInst->getOpcode(); in checkADDrr() local 111 if (Opcode == BPF::LDB || Opcode == BPF::LDH || Opcode == BPF::LDW || in checkADDrr() 112 Opcode == BPF::LDD || Opcode == BPF::STB || Opcode == BPF::STH || in checkADDrr() 113 Opcode == BPF::STW || Opcode == BPF::STD) in checkADDrr() 115 else if (Opcode == BPF::LDB32 || Opcode == BPF::LDH32 || in checkADDrr() 116 Opcode == BPF::LDW32 || Opcode == BPF::STB32 || in checkADDrr() 117 Opcode == BPF::STH32 || Opcode == BPF::STW32) in checkADDrr() 130 if (Opcode == BPF::STB || Opcode == BPF::STH || Opcode == BPF::STW || in checkADDrr() 131 Opcode == BPF::STD || Opcode == BPF::STB32 || Opcode == BPF::STH32 || in checkADDrr() [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZTargetTransformInfo.cpp | 66 InstructionCost SystemZTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst() argument 81 switch (Opcode) { in getIntImmCostInst() 384 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost() argument 392 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, in getArithmeticInstrCost() 413 Opcode == Instruction::SDiv || Opcode == Instruction::SRem; in getArithmeticInstrCost() 415 Opcode == Instruction::UDiv || Opcode == Instruction::URem; in getArithmeticInstrCost() 438 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub || in getArithmeticInstrCost() 439 Opcode == Instruction::FMul || Opcode == Instruction::FDiv) in getArithmeticInstrCost() 443 if (Opcode == Instruction::FRem) in getArithmeticInstrCost() 448 if (Opcode == Instruction::Xor) { in getArithmeticInstrCost() [all …]
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H A D | SystemZInstrInfo.cpp | 178 unsigned Opcode = getOpcodeForOffset( in expandRXYPseudo() local 181 MI.setDesc(get(Opcode)); in expandRXYPseudo() 190 unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode; in expandLOCPseudo() local 191 MI.setDesc(get(Opcode)); in expandLOCPseudo() 252 unsigned Opcode; in emitGRX32Move() local 256 Opcode = SystemZ::RISBHH; in emitGRX32Move() 258 Opcode = SystemZ::RISBHL; in emitGRX32Move() 260 Opcode = SystemZ::RISBLH; in emitGRX32Move() 266 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) in emitGRX32Move() 674 unsigned Opcode = MI.getOpcode(); in isPredicable() local [all …]
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H A D | SystemZShortenInst.cpp | 44 bool shortenOn0(MachineInstr &MI, unsigned Opcode); 45 bool shortenOn01(MachineInstr &MI, unsigned Opcode); 46 bool shortenOn001(MachineInstr &MI, unsigned Opcode); 47 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode); 48 bool shortenFPConv(MachineInstr &MI, unsigned Opcode); 49 bool shortenFusedFPOp(MachineInstr &MI, unsigned Opcode); 109 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) { in shortenOn0() argument 111 MI.setDesc(TII->get(Opcode)); in shortenOn0() 119 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) { in shortenOn01() argument 122 MI.setDesc(TII->get(Opcode)); in shortenOn01() [all …]
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/netbsd-src/external/apache2/llvm/dist/clang/lib/AST/Interp/ |
H A D | Opcodes.td | 1 //===--- Opcodes.td - Opcode defitions for the constexpr VM -----*- C++ -*-===// 92 class Opcode { 103 class AluOpcode : Opcode { 112 class JumpOpcode : Opcode { 130 def Ret : Opcode { 138 def RetVoid : Opcode { 144 def RetValue : Opcode { 150 def NoRet : Opcode {} 157 def Destroy : Opcode { 166 class ConstOpcode<Type Ty, ArgType ArgTy> : Opcode { [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetTransformInfo.cpp | 235 InstructionCost PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst() argument 240 return BaseT::getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst); in getIntImmCostInst() 251 switch (Opcode) { in getIntImmCostInst() 426 unsigned Opcode = 0; in mightUseCTR() local 494 case Intrinsic::fma: Opcode = ISD::FMA; break; in mightUseCTR() 495 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR() 496 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; in mightUseCTR() 497 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; in mightUseCTR() 498 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; in mightUseCTR() 499 case Intrinsic::rint: Opcode = ISD::FRINT; break; in mightUseCTR() [all …]
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H A D | PPCMIPeephole.cpp | 171 unsigned Opcode = MI->getOpcode(); in getKnownLeadingZeroCount() local 172 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec || in getKnownLeadingZeroCount() 173 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec) in getKnownLeadingZeroCount() 176 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) && in getKnownLeadingZeroCount() 180 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in getKnownLeadingZeroCount() 181 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec || in getKnownLeadingZeroCount() 182 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && in getKnownLeadingZeroCount() 186 if (Opcode == PPC::ANDI_rec) { in getKnownLeadingZeroCount() 191 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec || in getKnownLeadingZeroCount() 192 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec || in getKnownLeadingZeroCount() [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86AvoidStoreForwardingBlocks.cpp | 133 static bool isXMMLoadOpcode(unsigned Opcode) { in isXMMLoadOpcode() argument 134 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode() 135 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode() 136 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode() 137 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || in isXMMLoadOpcode() 138 Opcode == X86::VMOVUPSZ128rm || Opcode == X86::VMOVAPSZ128rm || in isXMMLoadOpcode() 139 Opcode == X86::VMOVUPDZ128rm || Opcode == X86::VMOVAPDZ128rm || in isXMMLoadOpcode() 140 Opcode == X86::VMOVDQU64Z128rm || Opcode == X86::VMOVDQA64Z128rm || in isXMMLoadOpcode() 141 Opcode == X86::VMOVDQU32Z128rm || Opcode == X86::VMOVDQA32Z128rm; in isXMMLoadOpcode() 143 static bool isYMMLoadOpcode(unsigned Opcode) { in isYMMLoadOpcode() argument [all …]
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H A D | X86TargetTransformInfo.h | 122 unsigned Opcode, Type *Ty, 133 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 137 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 141 InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, 146 InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, 151 getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, 154 InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, 183 unsigned Opcode, VectorType *Ty, bool IsPairwiseForm, 193 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 198 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
H A D | Instruction.h | 183 static inline bool isUnaryOp(unsigned Opcode) { 184 return Opcode >= UnaryOpsBegin && Opcode < UnaryOpsEnd; 186 static inline bool isBinaryOp(unsigned Opcode) { 187 return Opcode >= BinaryOpsBegin && Opcode < BinaryOpsEnd; 190 static inline bool isIntDivRem(unsigned Opcode) { 191 return Opcode == UDiv || Opcode == SDiv || Opcode == URem || Opcode == SRem; 195 static inline bool isShift(unsigned Opcode) { 196 return Opcode >= Shl && Opcode <= AShr; 210 static inline bool isBitwiseLogicOp(unsigned Opcode) { 211 return Opcode == And || Opcode == Or || Opcode == Xor; [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/ |
H A D | DWARFExpression.cpp | 124 Opcode = Data.getU8(&Offset); in extract() 126 Desc = getOpDesc(Opcode); in extract() 228 DIDumpOptions DumpOpts, uint8_t Opcode, in prettyPrintRegisterOp() argument 237 if (Opcode == DW_OP_bregx || Opcode == DW_OP_regx || in prettyPrintRegisterOp() 238 Opcode == DW_OP_regval_type) in prettyPrintRegisterOp() 240 else if (Opcode >= DW_OP_breg0 && Opcode < DW_OP_bregx) in prettyPrintRegisterOp() 241 DwarfRegNum = Opcode - DW_OP_breg0; in prettyPrintRegisterOp() 243 DwarfRegNum = Opcode - DW_OP_reg0; in prettyPrintRegisterOp() 247 if ((Opcode >= DW_OP_breg0 && Opcode <= DW_OP_breg31) || in prettyPrintRegisterOp() 248 Opcode == DW_OP_bregx) in prettyPrintRegisterOp() [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-readobj/ |
H A D | ARMEHABIPrinter.h | 99 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local 100 SW.startLine() << format("0x%02X ; vsp = vsp + %u\n", Opcode, in Decode_00xxxxxx() 101 ((Opcode & 0x3f) << 2) + 4); in Decode_00xxxxxx() 105 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local 106 SW.startLine() << format("0x%02X ; vsp = vsp - %u\n", Opcode, in Decode_01xxxxxx() 107 ((Opcode & 0x3f) << 2) + 4); in Decode_01xxxxxx() 124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local 125 SW.startLine() << format("0x%02X ; reserved (ARM MOVrr)\n", Opcode); in Decode_10011101() 129 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local 130 SW.startLine() << format("0x%02X ; reserved (WiMMX MOVrr)\n", Opcode); in Decode_10011111() [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | TargetOpcodes.h | 30 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode() argument 31 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START && in isPreISelGenericOpcode() 32 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isPreISelGenericOpcode() 36 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode() argument 37 return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isTargetSpecificOpcode() 42 inline bool isPreISelGenericOptimizationHint(unsigned Opcode) { in isPreISelGenericOptimizationHint() argument 43 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START && in isPreISelGenericOptimizationHint() 44 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END; in isPreISelGenericOptimizationHint()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerInfo.cpp | 88 OS << Opcode << ", Tys={"; in print() 94 OS << Opcode << ", MMOs={"; in print() 298 const unsigned Opcode = FirstOp + OpcodeIdx; in computeTables() local 334 setScalarAction(Opcode, TypeIdx, S(ScalarSpecifiedActions)); in computeTables() 344 Opcode, TypeIdx, PointerSpecifiedActions.first, in computeTables() 366 Opcode, TypeIdx, ElementSize, in computeTables() 377 Opcode, TypeIdx, VectorElementSizeChangeStrategy(ElementSizesSeen)); in computeTables() 412 unsigned LegalizerInfo::getOpcodeIdxForOpcode(unsigned Opcode) const { in getOpcodeIdxForOpcode() 413 assert(Opcode >= FirstOp && Opcode <= LastOp && "Unsupported opcode"); in getOpcodeIdxForOpcode() 414 return Opcode - FirstOp; in getOpcodeIdxForOpcode() [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonTargetTransformInfo.cpp | 159 InstructionCost HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost() argument 164 assert(Opcode == Instruction::Load || Opcode == Instruction::Store); in getMemoryOpCost() 169 if (Opcode == Instruction::Store) in getMemoryOpCost() 170 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, in getMemoryOpCost() 211 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, in getMemoryOpCost() 216 HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, in getMaskedMemoryOpCost() argument 219 return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace, in getMaskedMemoryOpCost() 230 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, in getGatherScatterOpCost() argument 232 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, in getGatherScatterOpCost() 237 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, in getInterleavedMemoryOpCost() argument [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 176 int Offset, unsigned Base, bool BaseKill, unsigned Opcode, 182 int Offset, unsigned Base, bool BaseKill, unsigned Opcode, 219 unsigned Opcode = MI.getOpcode(); in getMemoryOpOffset() local 220 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset() 224 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset() 225 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset() 226 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 || in getMemoryOpOffset() 227 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset() 231 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset() 232 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset() [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMUnwindOpAsm.h | 72 void EmitInt8(unsigned Opcode) { in EmitInt8() argument 73 Ops.push_back(Opcode & 0xff); in EmitInt8() 77 void EmitInt16(unsigned Opcode) { in EmitInt16() argument 78 Ops.push_back((Opcode >> 8) & 0xff); in EmitInt16() 79 Ops.push_back(Opcode & 0xff); in EmitInt16() 83 void emitBytes(const uint8_t *Opcode, size_t Size) { in emitBytes() argument 84 Ops.insert(Ops.end(), Opcode, Opcode + Size); in emitBytes()
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/netbsd-src/sys/external/bsd/acpica/dist/executer/ |
H A D | exoparg2.c | 105 AcpiPsGetOpcodeName (WalkState->Opcode)); in AcpiExOpcode_2A_0T_0R() 110 switch (WalkState->Opcode) in AcpiExOpcode_2A_0T_0R() 147 WalkState->Opcode)); in AcpiExOpcode_2A_0T_0R() 179 AcpiPsGetOpcodeName (WalkState->Opcode)); in AcpiExOpcode_2A_2T_1R() 184 switch (WalkState->Opcode) in AcpiExOpcode_2A_2T_1R() 220 WalkState->Opcode)); in AcpiExOpcode_2A_2T_1R() 290 AcpiPsGetOpcodeName (WalkState->Opcode)); in AcpiExOpcode_2A_1T_1R() 307 WalkState->Opcode, in AcpiExOpcode_2A_1T_1R() 313 switch (WalkState->Opcode) in AcpiExOpcode_2A_1T_1R() 486 WalkState->Opcode)); in AcpiExOpcode_2A_1T_1R() [all …]
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H A D | exoparg1.c | 100 AcpiPsGetOpcodeName (WalkState->Opcode)); in AcpiExOpcode_0A_0T_1R() 105 switch (WalkState->Opcode) in AcpiExOpcode_0A_0T_1R() 122 WalkState->Opcode)); in AcpiExOpcode_0A_0T_1R() 169 AcpiPsGetOpcodeName (WalkState->Opcode)); in AcpiExOpcode_1A_0T_0R() 174 switch (WalkState->Opcode) in AcpiExOpcode_1A_0T_0R() 209 WalkState->Opcode)); in AcpiExOpcode_1A_0T_0R() 241 AcpiPsGetOpcodeName (WalkState->Opcode)); in AcpiExOpcode_1A_1T_0R() 246 switch (WalkState->Opcode) in AcpiExOpcode_1A_1T_0R() 258 WalkState->Opcode)); in AcpiExOpcode_1A_1T_0R() 300 AcpiPsGetOpcodeName (WalkState->Opcode)); in AcpiExOpcode_1A_1T_1R() [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVTargetTransformInfo.cpp | 33 InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst() argument 49 switch (Opcode) { in getIntImmCostInst() 75 if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) { in getIntImmCostInst() 134 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, in getGatherScatterOpCost() argument 137 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, in getGatherScatterOpCost() 140 if ((Opcode == Instruction::Load && in getGatherScatterOpCost() 142 (Opcode == Instruction::Store && in getGatherScatterOpCost() 144 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, in getGatherScatterOpCost() 149 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, in getGatherScatterOpCost() 155 getMemoryOpCost(Opcode, VTy->getElementType(), Alignment, 0, CostKind, I); in getGatherScatterOpCost()
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H A D | RISCVInstrInfo.cpp | 254 unsigned Opcode; in storeRegToStackSlot() local 258 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? in storeRegToStackSlot() 262 Opcode = RISCV::FSH; in storeRegToStackSlot() 265 Opcode = RISCV::FSW; in storeRegToStackSlot() 268 Opcode = RISCV::FSD; in storeRegToStackSlot() 271 Opcode = RISCV::PseudoVSPILL_M1; in storeRegToStackSlot() 274 Opcode = RISCV::PseudoVSPILL_M2; in storeRegToStackSlot() 277 Opcode = RISCV::PseudoVSPILL_M4; in storeRegToStackSlot() 280 Opcode = RISCV::PseudoVSPILL_M8; in storeRegToStackSlot() 283 Opcode = RISCV::PseudoVSPILL2_M1; in storeRegToStackSlot() [all …]
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/netbsd-src/sys/external/bsd/acpica/dist/parser/ |
H A D | psutils.c | 100 UINT16 Opcode) in AcpiPsInitOp() argument 106 Op->Common.AmlOpcode = Opcode; in AcpiPsInitOp() 109 (AcpiPsGetOpcodeInfo (Opcode))->Name, in AcpiPsInitOp() 131 UINT16 Opcode, in AcpiPsAllocOp() argument 142 OpInfo = AcpiPsGetOpcodeInfo (Opcode); in AcpiPsAllocOp() 154 else if (Opcode == AML_INT_BYTELIST_OP) in AcpiPsAllocOp() 178 AcpiPsInitOp (Op, Opcode); in AcpiPsAllocOp() 183 if (Opcode == AML_SCOPE_OP) in AcpiPsAllocOp()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsDSPInstrFormats.td | 70 let Opcode = SPECIAL3_OPCODE.V; 83 let Opcode = SPECIAL3_OPCODE.V; 97 let Opcode = SPECIAL3_OPCODE.V; 111 let Opcode = SPECIAL3_OPCODE.V; 125 let Opcode = SPECIAL3_OPCODE.V; 139 let Opcode = SPECIAL3_OPCODE.V; 153 let Opcode = SPECIAL3_OPCODE.V; 167 let Opcode = SPECIAL3_OPCODE.V; 182 let Opcode = SPECIAL3_OPCODE.V; 197 let Opcode = SPECIAL3_OPCODE.V; [all …]
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