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Searched refs:OpRC (Results 1 – 8 of 8) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DBreakFalseDeps.cpp134 const TargetRegisterClass *OpRC = in pickBestRegisterForUndef() local
141 !OpRC->contains(CurrMO.getReg())) in pickBestRegisterForUndef()
153 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
H A DMachineInstr.cpp951 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
957 if (OpRC) in getRegClassConstraintEffect()
958 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
961 } else if (OpRC) in getRegClassConstraintEffect()
962 CurRC = TRI->getCommonSubClass(CurRC, OpRC); in getRegClassConstraintEffect()
H A DRegAllocFast.cpp1064 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg); in addRegClassDefCounts() local
1069 if (OpRC->hasSubClassEq(IdxRC)) in addRegClassDefCounts()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86SpeculativeLoadHardening.cpp1662 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr() local
1663 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
1667 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || in hardenLoadAddr()
1668 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { in hardenLoadAddr()
1670 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()
1684 Register VBStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
1704 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()
1705 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()
1706 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()
1708 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp320 const TargetRegisterClass *OpRC = nullptr; in AddRegisterOperand() local
322 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
324 if (OpRC) { in AddRegisterOperand()
326 = MRI->constrainRegClass(VReg, OpRC, MinRCSize); in AddRegisterOperand()
328 OpRC = TRI->getAllocatableClass(OpRC); in AddRegisterOperand()
329 assert(OpRC && "Constraints cannot be fulfilled for allocation"); in AddRegisterOperand()
330 Register NewVReg = MRI->createVirtualRegister(OpRC); in AddRegisterOperand()
389 const TargetRegisterClass *OpRC = in AddOperand() local
396 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) { in AddOperand()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp812 const TargetRegisterClass *OpRC = in processPHINode() local
814 if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass && in processPHINode()
815 OpRC != &AMDGPU::VS_64RegClass) { in processPHINode()
H A DSIInstrInfo.cpp5091 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand() local
5095 if (DstRC == OpRC) in legalizeGenericOperand()
5400 const TargetRegisterClass *OpRC = in legalizeOperands() local
5402 if (RI.hasVectorRegisters(OpRC)) { in legalizeOperands()
5403 VRC = OpRC; in legalizeOperands()
5405 SRC = OpRC; in legalizeOperands()
5462 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
5463 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
5464 if (VRC == OpRC) in legalizeOperands()
6922 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR() local
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp1886 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF); in validateReg() local
1888 return OpRC->hasSubClassEq(RRC); in validateReg()