| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 259 unsigned &Op3) { in Decode3OpInstruction() argument
269 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode3OpInstruction()
538 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
539 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RInstruction()
543 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RInstruction()
551 unsigned Op1, Op2, Op3; in Decode3RImmInstruction() local
552 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RImmInstruction()
556 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RImmInstruction()
564 unsigned Op1, Op2, Op3; in Decode2RUSInstruction() local
565 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode2RUSInstruction()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblySelectionDAGInfo.h | 27 SDValue Op3, Align Alignment, bool isVolatile,
33 SDValue Op1, SDValue Op2, SDValue Op3,
39 SDValue Op3, Align Alignment, bool IsVolatile,
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| H A D | WebAssemblySelectionDAGInfo.cpp | 38 SDValue Op3, Align Alignment, bool IsVolatile, in EmitTargetCodeForMemmove() argument
40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, in EmitTargetCodeForMemmove()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGTargetInfo.h | 53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove() argument
82 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
94 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
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| H A D | SelectionDAG.h | 1370 SDValue Op3);
1372 SDValue Op3, SDValue Op4);
1374 SDValue Op3, SDValue Op4, SDValue Op5);
1402 SDValue Op1, SDValue Op2, SDValue Op3);
1437 SDValue Op1, SDValue Op2, SDValue Op3);
1443 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
1450 SDValue Op3);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 110 const MachineOperand &Op3 = MI->getOperand(Operand + 3); in getAddressFromInstr() local
111 if (Op3.isGlobal()) in getAddressFromInstr()
112 AM.GV = Op3.getGlobal(); in getAddressFromInstr()
114 AM.Disp = Op3.getImm(); in getAddressFromInstr()
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| H A D | X86FastISel.cpp | 178 unsigned Op1, unsigned Op2, unsigned Op3);
3956 unsigned Op2, unsigned Op3) { in fastEmitInst_rrrr() argument
3963 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
3970 .addReg(Op3); in fastEmitInst_rrrr()
3976 .addReg(Op3); in fastEmitInst_rrrr()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreSelectionDAGInfo.h | 24 SDValue Op3, Align Alignment, bool isVolatile,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 271 BPFOperand &Op3 = (BPFOperand &)*Operands[3]; in PreMatchCheck() local
272 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck()
278 && Op0.getReg() != Op3.getReg()) in PreMatchCheck()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 334 : Pat<(vtd (op pg:$Op1, vts:$Op2, vtd:$Op3)),
335 (inst $Op3, $Op1, $Op2)>;
341 : Pat<(vtd (op pg:$Op1, vts:$Op2, (i64 timm0_1), vtd:$Op3)),
342 (inst $Op3, $Op1, $Op2)>;
377 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3)),
378 (inst $Op1, $Op2, $Op3)>;
383 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, vt4:$Op4)),
384 (inst $Op1, $Op2, $Op3, $Op4)>;
394 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, (vt3 ImmTy:$Op3))),
395 (inst $Op1, $Op2, ImmTy:$Op3)>;
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMSelectionDAGInfo.h | 57 SDValue Op3, Align Alignment, bool isVolatile,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 78 const MCOperand &Op3 = MI->getOperand(3); in printInst() local
82 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
85 switch (Op3.getImm()) { in printInst()
118 if (Op2.isImm() && Op3.isImm()) { in printInst()
122 int64_t imms = Op3.getImm(); in printInst()
152 if (Op2.getImm() > Op3.getImm()) { in printInst()
155 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
163 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | PatternMatch.h | 1454 T2 Op3; member
1456 ThreeOps_match(const T0 &Op1, const T1 &Op2, const T2 &Op3) in ThreeOps_match()
1457 : Op1(Op1), Op2(Op2), Op3(Op3) {} in ThreeOps_match()
1463 Op3.match(I->getOperand(2)); in match()
2132 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {
2133 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
2139 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3,
2141 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2, Op3),
2148 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3,
2150 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2, Op3, Op4),
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 4755 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
4756 if (Op2.isScalarReg() && Op3.isImm()) { in MatchAndEmitInstruction()
4757 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
4777 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext())); in MatchAndEmitInstruction()
4778 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3.getStartLoc(), in MatchAndEmitInstruction()
4779 Op3.getEndLoc(), getContext()); in MatchAndEmitInstruction()
4841 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
4844 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
4845 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
4860 return Error(Op3.getStartLoc(), in MatchAndEmitInstruction()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrFormats.td | 28 bit Op3 = 0;
54 let TSFlags{5} = Op3;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1257 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1261 Register Rt = Op3.getReg(); in expandPostRAPseudo()
1265 unsigned K3 = getKillRegState(Op3.isKill()); in expandPostRAPseudo()
1281 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1289 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill in expandPostRAPseudo()
1299 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
1303 .add(Op3); in expandPostRAPseudo()
1314 MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1322 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill in expandPostRAPseudo()
1335 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
[all …]
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| H A D | HexagonSplitDouble.cpp | 905 MachineOperand &Op3 = MI->getOperand(3); in splitAslOr() local
906 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
907 int64_t Sh64 = Op3.getImm(); in splitAslOr()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsTargetStreamer.h | 137 MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 227 unsigned Reg2, MCOperand Op3, SMLoc IDLoc, in emitRRRX() argument
234 TmpInst.addOperand(Op3); in emitRRRX()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 8207 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { in UpdateNodeOperands() argument
8208 SDValue Ops[] = { Op1, Op2, Op3 }; in UpdateNodeOperands()
8214 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
8215 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
8221 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
8222 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
8315 SDValue Op2, SDValue Op3) { in SelectNodeTo() argument
8317 SDValue Ops[] = { Op1, Op2, Op3 }; in SelectNodeTo()
8522 SDValue Op3) { in getMachineNode() argument
8524 SDValue Ops[] = { Op1, Op2, Op3 }; in getMachineNode()
[all …]
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| H A D | SelectionDAGBuilder.cpp | 5828 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
5838 SDValue MC = DAG.getMemcpy(Root, sdl, Op1, Op2, Op3, Alignment, isVol, in visitIntrinsicCall()
5870 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
5876 SDValue MS = DAG.getMemset(Root, sdl, Op1, Op2, Op3, Alignment, isVol, isTC, in visitIntrinsicCall()
5885 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
5895 SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Alignment, isVol, in visitIntrinsicCall()
6459 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6461 Op1.getValueType(), Op1, Op2, Op3)); in visitIntrinsicCall()
6470 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6472 Op1, Op2, Op3, DAG, TLI)); in visitIntrinsicCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 6622 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); in tryConvertingToTwoOperandForm() local
6624 if (!Op3.isReg() || !Op4.isReg()) in tryConvertingToTwoOperandForm()
6627 auto Op3Reg = Op3.getReg(); in tryConvertingToTwoOperandForm()
6945 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); in fixupGNULDRDAlias() local
6949 if (!Op3.isGPRMem()) in fixupGNULDRDAlias()
7027 const MCParsedAsmOperand &Op3 = *Operands[3 + NumPredOps]; in CDEConvertDualRegOperand() local
7028 if (!Op3.isReg() || Op3.getReg() != RNext) in CDEConvertDualRegOperand()
7029 return Error(Op3.getStartLoc(), "operand must be a consecutive register"); in CDEConvertDualRegOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/IR/ |
| H A D | Verifier.cpp | 5148 auto *Op3 = cast<ConstantInt>(Call.getArgOperand(2)); in visitIntrinsicCall() local
5149 Assert(Op3->getType()->getBitWidth() <= 32, in visitIntrinsicCall()
5155 Op3->getZExtValue() < Op1->getType()->getScalarSizeInBits(), in visitIntrinsicCall()
5159 Assert(Op3->getZExtValue() <= Op1->getType()->getScalarSizeInBits(), in visitIntrinsicCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | ConstantFolding.cpp | 2725 if (const auto *Op3 = dyn_cast<ConstantFP>(Operands[2])) { in ConstantFoldScalarCall3() local
2728 const APFloat &C3 = Op3->getValueAPF(); in ConstantFoldScalarCall3()
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/cp/ |
| H A D | cp-tree.def | 584 Op3 is a vector of the [0] e.ready, [1] e.suspend and [2] e.resume calls.
|