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Searched refs:OS_REG_WRITE (Results 1 – 25 of 62) sorted by relevance

123

/netbsd-src/sys/external/isc/atheros_hal/dist/ar5212/
H A Dar5212_keycache.c78 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); in ar5212ResetKeyCacheEntry()
79 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); in ar5212ResetKeyCacheEntry()
80 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); in ar5212ResetKeyCacheEntry()
81 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); in ar5212ResetKeyCacheEntry()
82 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); in ar5212ResetKeyCacheEntry()
83 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); in ar5212ResetKeyCacheEntry()
84 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); in ar5212ResetKeyCacheEntry()
85 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); in ar5212ResetKeyCacheEntry()
90 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); in ar5212ResetKeyCacheEntry()
91 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); in ar5212ResetKeyCacheEntry()
[all …]
H A Dar5212_beacon.c37 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt); in ar5212SetBeaconTimers()
38 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba); in ar5212SetBeaconTimers()
39 OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba); in ar5212SetBeaconTimers()
40 OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim); in ar5212SetBeaconTimers()
54 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_RESET_TSF); in ar5212SetBeaconTimers()
56 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval); in ar5212SetBeaconTimers()
109 OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */ in ar5212ResetStaBeaconTimers()
113 OS_REG_WRITE(ah, AR_STA_ID1, in ar5212ResetStaBeaconTimers()
115 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD); in ar5212ResetStaBeaconTimers()
133 OS_REG_WRITE(ah, AR_STA_ID1, in ar5212SetStaBeaconTimers()
[all …]
H A Dar5212_misc.c72 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); in ar5212SetBssIdMask()
73 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); in ar5212SetBssIdMask()
211 OS_REG_WRITE(ah, AR_PCICFG, bits); in ar5212SetLedState()
227 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); in ar5212WriteAssocid()
228 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) | in ar5212WriteAssocid()
278 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF); in ar5212ResetTsf()
286 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF); in ar5212ResetTsf()
317 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B); in ar5212SetBasicRate()
319 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B); in ar5212SetBasicRate()
363 OS_REG_WRITE(ah, AR_MIBC, in ar5212EnableMibCounters()
[all …]
H A Dar5212_recv.c43 OS_REG_WRITE(ah, AR_RXDP, rxdp); in ar5212SetRxDP()
53 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); in ar5212EnableReceive()
62 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5212StopDmaReceive()
85 OS_REG_WRITE(ah, AR_DIAG_SW, in ar5212StartPcuReceive()
98 OS_REG_WRITE(ah, AR_DIAG_SW, in ar5212StopPcuReceive()
110 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0); in ar5212SetMulticastFilter()
111 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1); in ar5212SetMulticastFilter()
126 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32)))); in ar5212ClrMulticastFilterIndex()
129 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix))); in ar5212ClrMulticastFilterIndex()
146 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32)))); in ar5212SetMulticastFilterIndex()
[all …]
H A Dar5212_reset.c79 OS_REG_WRITE(ah, reg, V(r, 1)); in write_common()
291 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar5212Reset()
315 OS_REG_WRITE(ah, AR_PHY_ADC_CTL, in ar5212Reset()
332 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, in ar5212Reset()
338 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0); in ar5212Reset()
348 OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); in ar5212Reset()
353 OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); in ar5212Reset()
365 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); in ar5212Reset()
373 OS_REG_WRITE(ah, AR_PHY_FAST_ADC, newReg); in ar5212Reset()
407 OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount); in ar5212Reset()
[all …]
H A Dar5212_xmit.c69 OS_REG_WRITE(ah, AR_TXCFG, in ar5212UpdateTxTrigLevel()
214 OS_REG_WRITE(ah, AR_IMR_S0, in setTxQInterrupts()
218 OS_REG_WRITE(ah, AR_IMR_S1, in setTxQInterrupts()
305 OS_REG_WRITE(ah, AR_DLCL_IFS(q), in ar5212ResetTxQueue()
311 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q), in ar5212ResetTxQueue()
333 OS_REG_WRITE(ah, AR_QCBRCFG(q), in ar5212ResetTxQueue()
341 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), in ar5212ResetTxQueue()
346 OS_REG_WRITE(ah, AR_DCHNTIME(q), in ar5212ResetTxQueue()
422 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_ENA); in ar5212ResetTxQueue()
431 OS_REG_WRITE(ah, AR_QMISC(q), qmisc); in ar5212ResetTxQueue()
[all …]
/netbsd-src/sys/external/isc/atheros_hal/dist/ar5312/
H A Dar5312_misc.c46 OS_REG_WRITE(ah, resOffset+AR5312_PCICFG, in ar5312SetLedState()
106 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f); in ar5312SetupClock()
107 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0d); in ar5312SetupClock()
108 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c); in ar5312SetupClock()
109 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03); in ar5312SetupClock()
110 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x05); in ar5312SetupClock()
111 OS_REG_WRITE(ah, AR_PHY_REFCLKPD, in ar5312SetupClock()
115 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */ in ar5312SetupClock()
118 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */ in ar5312SetupClock()
122 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f); in ar5312SetupClock()
[all …]
H A Dar5312_reset.c65 OS_REG_WRITE(ah, reg, V(i, 1)); in write_common()
250 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar5312Reset()
266 OS_REG_WRITE(ah, AR_PHY_ADC_CTL, in ar5312Reset()
280 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, in ar5312Reset()
284 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0); in ar5312Reset()
294 OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); in ar5312Reset()
299 OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); in ar5312Reset()
312 OS_REG_WRITE(ah, AR_PHY_SIGMA_DELTA, in ar5312Reset()
326 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04); in ar5312Reset()
333 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); in ar5312Reset()
[all …]
/netbsd-src/sys/external/isc/atheros_hal/dist/ar5210/
H A Dar5210_reset.c124 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); in ar5210Reset()
125 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)); in ar5210Reset()
130 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG); in ar5210Reset()
131 OS_REG_WRITE(ah, AR_PCICFG, in ar5210Reset()
135 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG | AR_BCR_BCMD); in ar5210Reset()
136 OS_REG_WRITE(ah, AR_PCICFG, in ar5210Reset()
140 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG); in ar5210Reset()
141 OS_REG_WRITE(ah, AR_PCICFG, in ar5210Reset()
145 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG); in ar5210Reset()
146 OS_REG_WRITE(ah, AR_PCICFG, in ar5210Reset()
[all …]
H A Dar5210_beacon.c36 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt); in ar5210SetBeaconTimers()
37 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba); in ar5210SetBeaconTimers()
38 OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba); in ar5210SetBeaconTimers()
39 OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim); in ar5210SetBeaconTimers()
43 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval); in ar5210SetBeaconTimers()
87 OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */ in ar5210ResetStaBeaconTimers()
91 OS_REG_WRITE(ah, AR_STA_ID1, in ar5210ResetStaBeaconTimers()
93 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD); in ar5210ResetStaBeaconTimers()
115 OS_REG_WRITE(ah, AR_STA_ID1, in ar5210SetStaBeaconTimers()
120 OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod); in ar5210SetStaBeaconTimers()
[all …]
H A Dar5210_keycache.c60 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); in ar5210ResetKeyCacheEntry()
61 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); in ar5210ResetKeyCacheEntry()
62 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); in ar5210ResetKeyCacheEntry()
63 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); in ar5210ResetKeyCacheEntry()
64 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); in ar5210ResetKeyCacheEntry()
65 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), 0); in ar5210ResetKeyCacheEntry()
66 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); in ar5210ResetKeyCacheEntry()
67 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); in ar5210ResetKeyCacheEntry()
97 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); in ar5210SetKeyCacheEntryMac()
98 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), in ar5210SetKeyCacheEntryMac()
[all …]
H A Dar5210_xmit.c181 OS_REG_WRITE(ah, AR_SLOT_TIME, INIT_SLOT_TIME_TURBO); in ar5210ResetTxQueue()
182 OS_REG_WRITE(ah, AR_TIME_OUT, INIT_ACK_CTS_TIMEOUT_TURBO); in ar5210ResetTxQueue()
183 OS_REG_WRITE(ah, AR_USEC, INIT_TRANSMIT_LATENCY_TURBO); in ar5210ResetTxQueue()
184 OS_REG_WRITE(ah, AR_IFS0, in ar5210ResetTxQueue()
188 OS_REG_WRITE(ah, AR_IFS1, INIT_PROTO_TIME_CNTRL_TURBO); in ar5210ResetTxQueue()
189 OS_REG_WRITE(ah, AR_PHY(17), in ar5210ResetTxQueue()
191 OS_REG_WRITE(ah, AR_PHY_FRCTL, in ar5210ResetTxQueue()
198 OS_REG_WRITE(ah, AR_SLOT_TIME, INIT_SLOT_TIME); in ar5210ResetTxQueue()
199 OS_REG_WRITE(ah, AR_TIME_OUT, INIT_ACK_CTS_TIMEOUT); in ar5210ResetTxQueue()
200 OS_REG_WRITE(ah, AR_USEC, INIT_TRANSMIT_LATENCY); in ar5210ResetTxQueue()
[all …]
H A Dar5210_recv.c44 OS_REG_WRITE(ah, AR_RXDP, rxdp); in ar5210SetRxDP()
54 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); in ar5210EnableReceive()
65 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5210StopDmaReceive()
85 OS_REG_WRITE(ah, AR_DIAG_SW, in ar5210StartPcuReceive()
95 OS_REG_WRITE(ah, AR_DIAG_SW, in ar5210StopPcuReceive()
106 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0); in ar5210SetMulticastFilter()
107 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1); in ar5210SetMulticastFilter()
122 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32)))); in ar5210ClrMulticastFilterIndex()
125 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix))); in ar5210ClrMulticastFilterIndex()
142 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32)))); in ar5210SetMulticastFilterIndex()
[all …]
H A Dar5210_misc.c165 OS_REG_WRITE(ah, AR_GPIOCR, in ar5210GpioCfgOutput()
180 OS_REG_WRITE(ah, AR_GPIOCR, in ar5210GpioCfgInput()
201 OS_REG_WRITE(ah, AR_GPIODO, reg); in ar5210GpioSet()
237 OS_REG_WRITE(ah, AR_GPIOCR, val); in ar5210Gpio0SetIntr()
266 OS_REG_WRITE(ah, AR_PCICFG, val); in ar5210SetLedState()
288 OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_DEFAULT_ANTENNA); in ar5210SetDefAntenna()
318 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); in ar5210WriteAssocid()
319 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) | in ar5210WriteAssocid()
372 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF); in ar5210ResetTsf()
456 OS_REG_WRITE(ah, AR_SLOT_TIME, ath_hal_mac_clks(ah, us)); in ar5210SetSlotTime()
[all …]
/netbsd-src/sys/external/isc/atheros_hal/dist/ar5416/
H A Dar5416_beacon.c40 OS_REG_WRITE(ah, AR_NEXT_TBTT, TU_TO_USEC(bt->bt_nexttbtt)); in ar5416SetBeaconTimers()
41 OS_REG_WRITE(ah, AR_NEXT_DBA, TU_TO_USEC(bt->bt_nextdba) >> 3); in ar5416SetBeaconTimers()
42 OS_REG_WRITE(ah, AR_NEXT_SWBA, TU_TO_USEC(bt->bt_nextswba) >> 3); in ar5416SetBeaconTimers()
43 OS_REG_WRITE(ah, AR_NEXT_NDP, TU_TO_USEC(bt->bt_nextatim)); in ar5416SetBeaconTimers()
46 OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, bperiod); in ar5416SetBeaconTimers()
47 OS_REG_WRITE(ah, AR_DBA_PERIOD, bperiod); in ar5416SetBeaconTimers()
48 OS_REG_WRITE(ah, AR_SWBA_PERIOD, bperiod); in ar5416SetBeaconTimers()
49 OS_REG_WRITE(ah, AR_NDP_PERIOD, bperiod); in ar5416SetBeaconTimers()
123 OS_REG_WRITE(ah, AR_NEXT_TBTT, 0); /* no beacons */ in ar5416ResetStaBeaconTimers()
127 OS_REG_WRITE(ah, AR_STA_ID1, in ar5416ResetStaBeaconTimers()
[all …]
H A Dar5416_reset.c194 OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg); in ar5416Reset()
204 OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); in ar5416Reset()
221 OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); in ar5416Reset()
225 OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); in ar5416Reset()
237 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); in ar5416Reset()
241 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); in ar5416Reset()
243 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, AH5416(ah)->ah_rx_chainmask); in ar5416Reset()
244 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, AH5416(ah)->ah_rx_chainmask); in ar5416Reset()
245 OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask); in ar5416Reset()
277 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); in ar5416Reset()
[all …]
H A Dar9280_attach.c186 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar9280Attach()
279 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); in ar9280Attach()
302 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); in ar9280ConfigPCIE()
330 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar9280WriteIni()
331 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); in ar9280WriteIni()
451 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); in ar9280SpurMitigate()
458 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); in ar9280SpurMitigate()
493 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); in ar9280SpurMitigate()
497 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); in ar9280SpurMitigate()
525 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar9280SpurMitigate()
[all …]
H A Dar5416_interrupts.c147 OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); in ar5416GetPendingInterrupts()
148 OS_REG_WRITE(ah, AR_RC, 0); in ar5416GetPendingInterrupts()
162 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); in ar5416GetPendingInterrupts()
185 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); in ar5416SetInterrupts()
188 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); in ar5416SetInterrupts()
191 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); in ar5416SetInterrupts()
241 OS_REG_WRITE(ah, AR_IMR, mask); in ar5416SetInterrupts()
250 OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2); in ar5416SetInterrupts()
257 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); in ar5416SetInterrupts()
259 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); in ar5416SetInterrupts()
[all …]
H A Dar5416_attach.c184 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); in ar5416GetRadioRev()
186 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); in ar5416GetRadioRev()
293 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar5416Attach()
352 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); in ar5416Attach()
409 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); in ar5416ConfigPCIE()
439 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar5416WriteIni()
444 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); in ar5416WriteIni()
451 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); in ar5416WriteIni()
522 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); in ar5416SpurMitigate()
529 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); in ar5416SpurMitigate()
[all …]
/netbsd-src/sys/external/isc/atheros_hal/dist/ar5211/
H A Dar5211_beacon.c39 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt); in ar5211SetBeaconTimers()
40 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba); in ar5211SetBeaconTimers()
41 OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba); in ar5211SetBeaconTimers()
42 OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim); in ar5211SetBeaconTimers()
46 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval); in ar5211SetBeaconTimers()
98 OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */ in ar5211ResetStaBeaconTimers()
102 OS_REG_WRITE(ah, AR_STA_ID1, in ar5211ResetStaBeaconTimers()
104 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD); in ar5211ResetStaBeaconTimers()
123 OS_REG_WRITE(ah, AR_STA_ID1, in ar5211SetStaBeaconTimers()
127 OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod); in ar5211SetStaBeaconTimers()
[all …]
H A Dar5211_keycache.c64 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); in ar5211ResetKeyCacheEntry()
65 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); in ar5211ResetKeyCacheEntry()
66 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); in ar5211ResetKeyCacheEntry()
67 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); in ar5211ResetKeyCacheEntry()
68 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); in ar5211ResetKeyCacheEntry()
69 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), 0); in ar5211ResetKeyCacheEntry()
70 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); in ar5211ResetKeyCacheEntry()
71 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); in ar5211ResetKeyCacheEntry()
106 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); in ar5211SetKeyCacheEntryMac()
107 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); in ar5211SetKeyCacheEntryMac()
[all …]
H A Dar5211_reset.c293 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007); in ar5211Reset()
295 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047); in ar5211Reset()
323 OS_REG_WRITE(ah, ar5211Mode2_4[i][0], in ar5211Reset()
332 OS_REG_WRITE(ah, ar5211Modes[i][0], ar5211Modes[i][modesIndex]); in ar5211Reset()
336 OS_REG_WRITE(ah, ar5211BB_RfGain[i][0], ar5211BB_RfGain[i][freqIndex]); in ar5211Reset()
343 OS_REG_WRITE(ah, reg, ar5211Common[i][1]); in ar5211Reset()
357 OS_REG_WRITE(ah, AR_USEC, in ar5211Reset()
361 OS_REG_WRITE(ah, AR5311_QDCLKGATE, 0); in ar5211Reset()
364 OS_REG_WRITE(ah, 0x00009878, 0x00000008); in ar5211Reset()
367 OS_REG_WRITE(ah, AR_DIAG_SW, in ar5211Reset()
[all …]
H A Dar5211_recv.c44 OS_REG_WRITE(ah, AR_RXDP, rxdp); in ar5211SetRxDP()
55 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); in ar5211EnableReceive()
64 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5211StopDmaReceive()
86 OS_REG_WRITE(ah, AR_DIAG_SW, in ar5211StartPcuReceive()
96 OS_REG_WRITE(ah, AR_DIAG_SW, in ar5211StopPcuReceive()
107 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0); in ar5211SetMulticastFilter()
108 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1); in ar5211SetMulticastFilter()
123 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32)))); in ar5211ClrMulticastFilterIndex()
126 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix))); in ar5211ClrMulticastFilterIndex()
143 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32)))); in ar5211SetMulticastFilterIndex()
[all …]
H A Dar5211_xmit.c67 OS_REG_WRITE(ah, AR_TXCFG, (txcfg &~ AR_TXCFG_FTRIG_M) | in ar5211UpdateTxTrigLevel()
182 OS_REG_WRITE(ah, AR_IMR_S0, in setTxQInterrupts()
186 OS_REG_WRITE(ah, AR_IMR_S1, in setTxQInterrupts()
268 OS_REG_WRITE(ah, AR_DLCL_IFS(q), in ar5211ResetTxQueue()
274 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q), in ar5211ResetTxQueue()
282 OS_REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ); in ar5211ResetTxQueue()
286 OS_REG_WRITE(ah, AR_DMISC(q), AR5311_D_MISC_SEQ_NUM_CONTROL); in ar5211ResetTxQueue()
290 OS_REG_WRITE(ah, AR_QCBRCFG(q), in ar5211ResetTxQueue()
293 OS_REG_WRITE(ah, AR_QMISC(q), in ar5211ResetTxQueue()
300 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), in ar5211ResetTxQueue()
[all …]
H A Dar5211_misc.c70 OS_REG_WRITE(ah, AR_EEPROM_ADDR, off); in ar5211EepromRead()
71 OS_REG_WRITE(ah, AR_EEPROM_CMD, AR_EEPROM_CMD_READ); in ar5211EepromRead()
205 OS_REG_WRITE(ah, AR_GPIOCR, reg); in ar5211GpioCfgOutput()
223 OS_REG_WRITE(ah, AR_GPIOCR, reg); in ar5211GpioCfgInput()
241 OS_REG_WRITE(ah, AR_GPIODO, reg); in ar5211GpioSet()
277 OS_REG_WRITE(ah, AR_GPIOCR, val); in ar5211GpioSetIntr()
299 OS_REG_WRITE(ah, AR_PCICFG, in ar5211SetLedState()
319 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); in ar5211WriteAssocid()
320 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) | in ar5211WriteAssocid()
369 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF); in ar5211ResetTsf()
[all …]

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