Home
last modified time | relevance | path

Searched refs:OPENPIC_BASE (Results 1 – 5 of 5) sorted by relevance

/netbsd-src/sys/arch/evbppc/mpc85xx/
H A Dmachdep.c1002 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ in e500_cpu_hatch()
1210 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); in initppc()
1211 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) in initppc()
1214 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ in initppc()
1217 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); in initppc()
/netbsd-src/sys/arch/powerpc/booke/
H A De500_timer.c74 OPENPIC_BASE + offset, val); in openpic_write()
H A De500_intr.c465 OPENPIC_BASE + offset); in openpic_read()
473 OPENPIC_BASE + offset, val); in openpic_write()
/netbsd-src/sys/arch/powerpc/include/booke/
H A De500reg.h271 #define OPENPIC_BASE 0x40000 macro
/netbsd-src/sys/arch/powerpc/booke/pci/
H A Dpq3pci.c1167 msig->msig_msir = OPENPIC_BASE + OPENPIC_MSIR(msig->msig_group); in pq3pci_msi_group_setup()
1481 sc->sc_bst->pbs_offset + OPENPIC_BASE + OPENPIC_MSIIR); in pq3pci_intr_establish()