| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 241 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
248 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
250 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
252 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
253 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
254 void SelectPredicatedLoad(SDNode *N, unsigned NumVecs, unsigned Scale,
268 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
269 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
270 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
271 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
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| H A D | AArch64ISelLowering.cpp | 10782 template <unsigned NumVecs>
10792 for (unsigned I = 0; I < NumVecs; ++I) in setInfoSVEStN()
10798 EC * NumVecs); in setInfoSVEStN()
14850 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
14855 NumVecs = 2; break; in performNEONPostLDSTCombine()
14857 NumVecs = 3; break; in performNEONPostLDSTCombine()
14859 NumVecs = 4; break; in performNEONPostLDSTCombine()
14861 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
14863 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
14865 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 203 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
211 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
219 unsigned NumVecs, const uint16_t *DOpcodes,
276 void SelectMVE_VLD(SDNode *N, unsigned NumVecs,
297 unsigned NumVecs, const uint16_t *DOpcodes,
335 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1921 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1922 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1923 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2068 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement() argument
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| H A D | ARMISelLowering.cpp | 14634 unsigned NumVecs = 0; in CombineBaseUpdate() local
14640 NumVecs = 1; break; in CombineBaseUpdate()
14642 NumVecs = 2; break; in CombineBaseUpdate()
14644 NumVecs = 3; break; in CombineBaseUpdate()
14646 NumVecs = 4; break; in CombineBaseUpdate()
14657 NumVecs = 2; isLaneOp = true; break; in CombineBaseUpdate()
14659 NumVecs = 3; isLaneOp = true; break; in CombineBaseUpdate()
14661 NumVecs = 4; isLaneOp = true; break; in CombineBaseUpdate()
14663 NumVecs = 1; isLoadOp = false; break; in CombineBaseUpdate()
14665 NumVecs = 2; isLoadOp = false; break; in CombineBaseUpdate()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 786 unsigned NumVecs) { in createInterleaveMask() argument
789 for (unsigned j = 0; j < NumVecs; j++) in createInterleaveMask()
844 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
845 assert(NumVecs > 1 && "Should be at least two vectors"); in concatenateVectors()
851 for (unsigned i = 0; i < NumVecs - 1; i += 2) { in concatenateVectors()
853 assert((V0->getType() == V1->getType() || i == NumVecs - 2) && in concatenateVectors()
860 if (NumVecs % 2 != 0) in concatenateVectors()
861 TmpList.push_back(ResList[NumVecs - 1]); in concatenateVectors()
864 NumVecs = ResList.size(); in concatenateVectors()
865 } while (NumVecs > 1); in concatenateVectors()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/ |
| H A D | VectorUtils.h | 502 llvm::SmallVector<int, 16> createInterleaveMask(unsigned VF, unsigned NumVecs);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 10310 int NumVecs = 2; in LowerINTRINSIC_WO_CHAIN() local
10313 NumVecs = 4; in LowerINTRINSIC_WO_CHAIN()
10317 for (int VecNo = 0; VecNo < NumVecs; VecNo++) { in LowerINTRINSIC_WO_CHAIN()
10320 DAG.getConstant(Subtarget.isLittleEndian() ? NumVecs - 1 - VecNo in LowerINTRINSIC_WO_CHAIN()
10560 unsigned NumVecs = VT.getSizeInBits() / 128; in LowerVectorLoad() local
10561 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerVectorLoad()
10605 unsigned NumVecs = 2; in LowerVectorStore() local
10608 NumVecs = 4; in LowerVectorStore()
10610 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerVectorStore()
10611 unsigned VecNum = Subtarget.isLittleEndian() ? NumVecs - 1 - Idx : Idx; in LowerVectorStore()
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 15363 unsigned NumVecs = 2; in EmitPPCBuiltinExpr() local
15366 NumVecs = 4; in EmitPPCBuiltinExpr()
15375 for (unsigned i=0; i<NumVecs; i++) { in EmitPPCBuiltinExpr()
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