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Searched refs:NewOpcode (Results 1 – 25 of 40) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp85 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
88 NewOpcode = Hexagon::J2_jumpf; in InvertAndChangeJumpTarget()
91 NewOpcode = Hexagon::J2_jumpt; in InvertAndChangeJumpTarget()
94 NewOpcode = Hexagon::J2_jumpfnewpt; in InvertAndChangeJumpTarget()
97 NewOpcode = Hexagon::J2_jumptnewpt; in InvertAndChangeJumpTarget()
103 MI.setDesc(TII->get(NewOpcode)); in InvertAndChangeJumpTarget()
H A DHexagonVLIWPacketizer.cpp463 int NewOpcode; in promoteToDotNew() local
465 NewOpcode = HII->getDotNewPredOp(MI, MBPI); in promoteToDotNew()
467 NewOpcode = HII->getDotNewOp(MI); in promoteToDotNew()
468 MI.setDesc(HII->get(NewOpcode)); in promoteToDotNew()
473 int NewOpcode = HII->getDotOldOp(MI); in demoteToDotOld() local
474 MI.setDesc(HII->get(NewOpcode)); in demoteToDotOld()
892 int NewOpcode = HII->getDotNewOp(MI); in canPromoteToDotNew() local
893 const MCInstrDesc &D = HII->get(NewOpcode); in canPromoteToDotNew()
H A DHexagonInstrInfo.cpp1557 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode); in reverseBranchCondition() local
1558 Cond[0].setImm(NewOpcode); in reverseBranchCondition()
3759 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode()); in getDotNewPredOp() local
3760 if (NewOpcode >= 0) in getDotNewPredOp()
3761 return NewOpcode; in getDotNewPredOp()
4553 unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode()); in invertAndChangeJumpTarget() local
4562 NewOpcode = reversePrediction(NewOpcode); in invertAndChangeJumpTarget()
4564 MI.setDesc(get(NewOpcode)); in invertAndChangeJumpTarget()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DMVEVPTBlockPass.cpp68 unsigned &NewOpcode) { in findVCMPToFoldIntoVPST() argument
83 NewOpcode = VCMPOpcodeToVPT(CmpMI->getOpcode()); in findVCMPToFoldIntoVPST()
84 if (NewOpcode == 0) in findVCMPToFoldIntoVPST()
264 unsigned NewOpcode; in InsertVPTBlocks() local
266 if (MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, TRI, NewOpcode)) { in InsertVPTBlocks()
268 MIBuilder = BuildMI(Block, MI, DL, TII->get(NewOpcode)); in InsertVPTBlocks()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp137 int NewOpcode; in InsertSPImmInst() local
139 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in InsertSPImmInst()
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
145 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in InsertSPImmInst()
146 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
152 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in InsertSPImmInst()
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp405 unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode()); in optTwoAddrLEA() local
411 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
416 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
428 unsigned NewOpcode = getINCDECFromLEA(MI.getOpcode(), IsINC); in optTwoAddrLEA() local
432 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
435 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
439 unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp); in optTwoAddrLEA() local
442 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
446 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
H A DX86InstrInfo.cpp4164 unsigned NewOpcode = 0; in optimizeCompareInstr() local
4167 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; in optimizeCompareInstr()
4168 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; in optimizeCompareInstr()
4169 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; in optimizeCompareInstr()
4170 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; in optimizeCompareInstr()
4171 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; in optimizeCompareInstr()
4172 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; in optimizeCompareInstr()
4173 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; in optimizeCompareInstr()
4174 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; in optimizeCompareInstr()
4175 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; in optimizeCompareInstr()
[all …]
H A DX86MCInstLower.cpp343 unsigned NewOpcode = 0; in SimplifyMOVSX() local
350 NewOpcode = X86::CBW; in SimplifyMOVSX()
354 NewOpcode = X86::CWDE; in SimplifyMOVSX()
358 NewOpcode = X86::CDQE; in SimplifyMOVSX()
362 if (NewOpcode != 0) { in SimplifyMOVSX()
364 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp100 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
253 int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode()); in tryToCombine() local
254 assert(NewOpcode > 0 && "No postincrement form found"); in tryToCombine()
256 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2)); in tryToCombine()
441 void ARCOptAddrMode::changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode, in changeToAddrMode() argument
459 Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode)); in changeToAddrMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDILCFGStructurizer.cpp197 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
199 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
201 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
202 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
205 MachineBasicBlock::iterator I, int NewOpcode,
432 int NewOpcode, const DebugLoc &DL) { in insertInstrEnd() argument
434 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
441 int NewOpcode, in insertInstrBefore() argument
444 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
454 MachineBasicBlock::iterator I, int NewOpcode) { in insertInstrBefore() argument
[all …]
H A DSIWholeQuadMode.cpp744 unsigned NewOpcode = 0; in splitBlock() local
747 NewOpcode = AMDGPU::S_AND_B32_term; in splitBlock()
750 NewOpcode = AMDGPU::S_AND_B64_term; in splitBlock()
753 NewOpcode = AMDGPU::S_MOV_B32_term; in splitBlock()
756 NewOpcode = AMDGPU::S_MOV_B64_term; in splitBlock()
761 if (NewOpcode) in splitBlock()
762 TermMI->setDesc(TII->get(NewOpcode)); in splitBlock()
H A DSIISelLowering.h74 unsigned NewOpcode) const;
76 unsigned NewOpcode) const;
H A DSIShrinkInstructions.cpp286 unsigned NewOpcode = in shrinkMIMG() local
289 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp193 int NewOpcode = -1; in encodeInstruction() local
196 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
197 if (NewOpcode == -1) in encodeInstruction()
198 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
201 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); in encodeInstruction()
204 if (NewOpcode == -1) in encodeInstruction()
205 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); in encodeInstruction()
207 if (NewOpcode != -1) { in encodeInstruction()
211 TmpInst.setOpcode (NewOpcode); in encodeInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.cpp228 unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode()); in eliminateFrameIndex() local
233 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode), in eliminateFrameIndex()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp601 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue() local
605 if (!NewOpcode) { in emitEpilogue()
610 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
611 assert(NewOpcode && "No restore instruction available"); in emitEpilogue()
614 MBBI->setDesc(ZII->get(NewOpcode)); in emitEpilogue()
H A DSystemZInstrInfo.cpp66 unsigned NewOpcode) const { in splitMove()
107 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
108 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
125 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc() local
126 assert(NewOpcode && "No support for huge argument lists yet"); in splitAdjDynAlloc()
127 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
957 unsigned NewOpcode; in convertToThreeAddress() local
959 NewOpcode = SystemZ::RISBG; in convertToThreeAddress()
962 NewOpcode = SystemZ::RISBGN; in convertToThreeAddress()
964 NewOpcode = SystemZ::RISBMux; in convertToThreeAddress()
[all …]
H A DSystemZInstrInfo.h178 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp1508 std::string NewOpcode; in ParseInstruction() local
1510 NewOpcode = std::string(Name); in ParseInstruction()
1511 NewOpcode += '+'; in ParseInstruction()
1512 Name = NewOpcode; in ParseInstruction()
1515 NewOpcode = std::string(Name); in ParseInstruction()
1516 NewOpcode += '-'; in ParseInstruction()
1517 Name = NewOpcode; in ParseInstruction()
1523 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
1531 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp468 int NewOpcode; in expand_DestructiveOp() local
470 if ((NewOpcode = AArch64::getSVERevInstr(Opcode)) != -1) in expand_DestructiveOp()
471 Opcode = NewOpcode; in expand_DestructiveOp()
473 else if ((NewOpcode = AArch64::getSVENonRevInstr(Opcode)) != -1) in expand_DestructiveOp()
474 Opcode = NewOpcode; in expand_DestructiveOp()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp758 int NewOpcode = in convertMIMGInst() local
760 if (NewOpcode == -1) in convertMIMGInst()
766 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; in convertMIMGInst()
789 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; in convertMIMGInst()
796 MI.setOpcode(NewOpcode); in convertMIMGInst()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp6857 unsigned NewOpcode; in PeepholePPC64ZExt() local
6861 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break; in PeepholePPC64ZExt()
6862 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break; in PeepholePPC64ZExt()
6863 case PPC::SLW: NewOpcode = PPC::SLW8; break; in PeepholePPC64ZExt()
6864 case PPC::SRW: NewOpcode = PPC::SRW8; break; in PeepholePPC64ZExt()
6865 case PPC::LI: NewOpcode = PPC::LI8; break; in PeepholePPC64ZExt()
6866 case PPC::LIS: NewOpcode = PPC::LIS8; break; in PeepholePPC64ZExt()
6867 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break; in PeepholePPC64ZExt()
6868 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break; in PeepholePPC64ZExt()
6869 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break; in PeepholePPC64ZExt()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp565 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); in replaceWithCompactBranch() local
566 Branch = TII->genInstrWithNewOpc(NewOpcode, Branch); in replaceWithCompactBranch()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h827 int64_t NewOpcode = MatchTable[CurrentIdx++]; in executeMatchTable() local
833 OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode)); in executeMatchTable()
837 << NewOpcode << ")\n"); in executeMatchTable()
H A DLegalizerHelper.h250 void changeOpcode(MachineInstr &MI, unsigned NewOpcode);

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