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Searched refs:NV_CIO_CRE_LCD__INDEX (Results 1 – 6 of 6) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/
H A Dnouveau_dispnv04_tvnv04.c121 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_LCD__INDEX, in nv04_tv_bind()
122 state->CRTC[NV_CIO_CRE_LCD__INDEX]); in nv04_tv_bind()
H A Dnouveau_dispnv04_dfp.c114 crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &= in nv04_dfp_disable()
256 uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX]; in nv04_dfp_prepare()
257 uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX]; in nv04_dfp_prepare()
276 NV_CIO_CRE_LCD__INDEX, in nv04_dfp_prepare()
H A Dnvreg.h267 # define NV_CIO_CRE_LCD__INDEX 0x33 macro
H A Dnouveau_dispnv04_hw.c640 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); in nv_save_state_ext()
759 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); in nv_load_state_ext()
H A Dnouveau_dispnv04_crtc.c680 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; in nv_crtc_save()
H A Dnouveau_dispnv04_tvnv17.c409 NV_CIO_CRE_LCD__INDEX]; in nv17_tv_prepare()