Searched refs:NUM_UCLK_DPM_LEVELS (Results 1 – 12 of 12) sorted by relevance
43 #define NUM_UCLK_DPM_LEVELS 4 macro52 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)222 uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */223 PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS]; /* Full PLL settings */224 uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
47 #define NUM_UCLK_DPM_LEVELS 4 macro62 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)590 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz600 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, …605 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)606 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
41 #define NUM_UCLK_DPM_LEVELS 4 macro51 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)517 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
44 #define NUM_UCLK_DPM_LEVELS 4 macro59 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)426 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
42 #define NUM_UCLK_DPM_LEVELS 4 macro55 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)314 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
338 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1841 while (i < NUM_UCLK_DPM_LEVELS) { in vega10_populate_all_memory_levels()3523 return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1; in vega10_get_soc_index_for_max_uclk()3548 if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) in vega10_upload_dpm_bootup_level()
2346 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, in vega12_set_uclk_to_highest_dpm_level()
3497 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, in vega20_set_uclk_to_highest_dpm_level()
636 dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1]; in navi10_set_default_dpm_table()
1722 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in arcturus_dump_pptable()
2031 if (dpm_table->count > NUM_UCLK_DPM_LEVELS) { in vega20_set_uclk_to_highest_dpm_level()