| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFMCInstLower.cpp | 71 case MachineOperand::MO_RegisterMask: in Lower()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcMCInstLower.cpp | 87 case MachineOperand::MO_RegisterMask: break; in LowerOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEMCInstLower.cpp | 71 case MachineOperand::MO_RegisterMask: in LowerOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 64 MO_RegisterMask, ///< Mask of preserved registers. enumerator
345 bool isRegMask() const { return OpKind == MO_RegisterMask; } in isRegMask()
888 MachineOperand Op(MachineOperand::MO_RegisterMask); in CreateRegMask()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRMCInstLower.cpp | 92 case MachineOperand::MO_RegisterMask: in lowerInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| H A D | ARCMCInstLower.cpp | 97 case MachineOperand::MO_RegisterMask: in LowerOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreMCInstLower.cpp | 96 case MachineOperand::MO_RegisterMask: in LowerOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiMCInstLower.cpp | 114 case MachineOperand::MO_RegisterMask: in Lower()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430MCInstLower.cpp | 153 case MachineOperand::MO_RegisterMask: in Lower()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kMCInstLower.cpp | 139 case MachineOperand::MO_RegisterMask: in LowerOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineStableHash.cpp | 117 case MachineOperand::MO_RegisterMask: in stableHashValue()
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| H A D | MIRVRegNamerUtils.cpp | 111 case MachineOperand::MO_RegisterMask: in getInstructionOpcodeHash()
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| H A D | MachineOperand.cpp | 314 case MachineOperand::MO_RegisterMask: in isIdenticalTo()
381 case MachineOperand::MO_RegisterMask: in hash_value()
870 case MachineOperand::MO_RegisterMask: { in print()
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| H A D | MIRPrinter.cpp | 886 case MachineOperand::MO_RegisterMask: { in print()
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| H A D | MachineVerifier.cpp | 2034 case MachineOperand::MO_RegisterMask: in visitMachineOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonMCInstLower.cpp | 121 case MachineOperand::MO_RegisterMask: in HexagonLowerToMC()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMMCInstLower.cpp | 116 case MachineOperand::MO_RegisterMask: in lowerOperand()
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| H A D | ARMExpandPseudoInsts.cpp | 863 case MachineOperand::MO_RegisterMask: in IsAnAddressOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCMCInstLower.cpp | 201 case MachineOperand::MO_RegisterMask: in LowerPPCMachineOperandToMCOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVMCInstLower.cpp | 102 case MachineOperand::MO_RegisterMask: in LowerRISCVMachineOperandToMCOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsMCInstLower.cpp | 197 case MachineOperand::MO_RegisterMask: in LowerOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64MCInstLower.cpp | 269 case MachineOperand::MO_RegisterMask: in lowerOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUMCInstLower.cpp | 168 case MachineOperand::MO_RegisterMask: in lowerOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 451 case MachineOperand::MO_RegisterMask: in LowerMachineOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/ |
| H A D | CodeGenerator.rst | 477 possible to use an ``MO_RegisterMask`` operand instead. The register mask
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