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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrMMX.td1 //===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===//
9 // This file describes the X86 MMX instruction set, defining the instructions,
13 // All instructions that use MMX should be in this file, even if they also use
19 // MMX Multiclasses
33 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
73 /// Unary MMX instructions requiring SSSE3.
87 /// Binary MMX instructions requiring SSSE3.
107 /// PALIGN MMX instructions (require SSSE3).
148 // MMX EMMS Instruction
157 // MMX Scalar Instructions
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H A DX86Instr3DNow.td9 // This file describes the 3DNow! instruction set, which extends MMX to support
56 defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb", SchedWriteVecALU.MMX, 1>;
74 defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", SchedWriteVecIMul.MMX, 1>;
112 defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", SchedWriteShuffle.MMX, "a">;
H A DX86InstrFormats.td553 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
621 // MMX operands.
623 // MMX operands.
695 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
696 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
699 // uses the MMX registers. The 64-bit versions are grouped with the MMX
978 // MMX Instruction templates
981 // MMXI - MMX instructions with TB prefix.
982 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
983 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
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/netbsd-src/external/lgpl3/gmp/dist/mpn/x86/k6/
H A DREADME39 The mmx subdirectory has MMX code suiting plain K6, the k62mmx subdirectory
40 has MMX code suiting K6-2 and K6-3. All chips in the K6 family have MMX,
42 assembler doesn't support MMX.
72 K6-2 and K6-3 have dual-issue MMX and get the following improvements.
88 All K6 family chips have MMX, but only K6-2 and K6-3 have 3DNow.
90 Plain K6 executes MMX instructions only in the X pipe, but K6-2 and K6-3 can
127 MMX
130 Perhaps an emms or femms stalls until all outstanding MMX instructions have
180 This affects all MMX and 3DNow instructions, and others with an 0F prefix,
226 "AMD-K6 MMX Enhanced Processor x86 Code Optimization Application Note", AMD
/netbsd-src/external/gpl3/gcc/dist/gcc/config/i386/
H A Di386.opt659 Support MMX built-in functions.
671 Support MMX and SSE built-in functions and code generation.
675 Support MMX, SSE and SSE2 built-in functions and code generation.
679 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation.
683 Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation.
687 Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation.
691 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
695 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
707 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation.
711 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code gener…
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H A Dpentium.md32 ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
33 ;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
34 ;; rules, because it results in noticeably better code on non-MMX Pentium
35 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/i386/
H A Di386.opt643 Support MMX built-in functions.
655 Support MMX and SSE built-in functions and code generation.
659 Support MMX, SSE and SSE2 built-in functions and code generation.
663 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation.
667 Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation.
671 Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation.
675 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
679 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
691 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation.
695 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code gener…
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H A Dpentium.md32 ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
33 ;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
34 ;; rules, because it results in noticeably better code on non-MMX Pentium
35 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
/netbsd-src/external/lgpl3/gmp/dist/mpn/x86/pentium/
H A DREADME37 processors. The mmx subdirectory has additional code for Pentium with MMX
64 Pentium MMX gets the following improvements
81 P55 MMX AND X87
83 The cost of switching between MMX and x87 floating point on P55 is about 100
85 mixed and currently that means using MMX and not x87.
87 MMX offers a big speedup for lshift and rshift, and a nice speedup for
89 perhaps the preference for MMX will be reversed.
/netbsd-src/external/lgpl3/gmp/dist/mpn/x86/k7/
H A DREADME37 The mmx subdirectory has routines using MMX instructions. All Athlons have
38 MMX, the separate directory is just so that configure can omit it if the
39 assembler doesn't support MMX.
72 cmov, MMX, 3DNow and some extensions to MMX and 3DNow are available.
154 "AMD Extensions to the 3DNow and MMX Instruction Sets Manual", AMD
/netbsd-src/external/lgpl3/gmp/dist/mpn/x86/pentium/mmx/
H A Dmul_1.asm1 dnl Intel Pentium MMX mpn_mul_1 -- mpn by limb multiplication.
51 C MMX is not believed to be of any use for 32-bit multipliers, since for
57 C Adding the high and low MMX products using integer code seems best. An
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/arm/iwmmxt/
H A Dwzero.cgs1 # Intel(r) Wireless MMX(tm) technology testcase for WZERO
H A Dtmiaph.cgs1 # Intel(r) Wireless MMX(tm) technology testcase for TMIAPH
H A Dtmia.cgs1 # Intel(r) Wireless MMX(tm) technology testcase for TMIA
H A Dwmov.cgs1 # Intel(r) Wireless MMX(tm) technology testcase for WMOV
H A Dwshufh.cgs1 # Intel(r) Wireless MMX(tm) technology testcase for WSHUFH
H A Dwandn.cgs1 # Intel(r) Wireless MMX(tm) technology testcase for WANDN
H A Dwor.cgs1 # Intel(r) Wireless MMX(tm) technology testcase for WOR
H A Dwxor.cgs1 # Intel(r) Wireless MMX(tm) technology testcase for WXOR
H A Dwand.cgs1 # Intel(r) Wireless MMX(tm) technology testcase for WAND
H A Dwaligni.cgs1 # Intel(r) Wireless MMX(tm) technology testcase for WALIGNI
H A Dtbcst.cgs1 # Intel(r) Wireless MMX(tm) technology testcase for TBCST
H A Dtinsr.cgs1 # Intel(r) Wireless MMX(tm) technology testcase for TINSR
/netbsd-src/external/lgpl3/gmp/dist/mpn/x86/p6/
H A DREADME39 have routines using MMX instructions.
68 Pentium II and III have MMX and get the following improvements.
/netbsd-src/external/lgpl3/gmp/dist/mpn/x86/pentium4/
H A DREADME37 The mmx subdirectory has routines using MMX instructions, the sse2
94 The movq however executes in the float unit, thereby saving MMX execution

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