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Searched refs:MI_INSTR (Results 1 – 3 of 3) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gt/
H A Dintel_gpu_commands.h37 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) macro
41 #define MI_NOOP MI_INSTR(0, 0)
42 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
43 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
48 #define MI_FLUSH MI_INSTR(0x04, 0)
55 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
56 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
59 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
60 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
62 #define MI_SET_APPID MI_INSTR(0x0e, 0)
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H A Dselftest_lrc.c3694 if ((lri & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) { in live_lrc_layout()
/netbsd-src/sys/external/bsd/drm/dist/shared-core/
H A Di915_reg.h108 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) macro
110 #define MI_NOOP MI_INSTR(0, 0)
111 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
112 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
116 #define MI_FLUSH MI_INSTR(0x04, 0)
122 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
123 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
124 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
125 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
127 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
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