Home
last modified time | relevance | path

Searched refs:LogicOpcode (Results 1 – 3 of 3) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1807 unsigned LogicOpcode = LogicMI->getOpcode(); in matchShiftOfShiftedLogic() local
1808 if (LogicOpcode != TargetOpcode::G_AND && LogicOpcode != TargetOpcode::G_OR && in matchShiftOfShiftedLogic()
1809 LogicOpcode != TargetOpcode::G_XOR) in matchShiftOfShiftedLogic()
2871 unsigned LogicOpcode = MI.getOpcode(); in matchHoistLogicOpWithSameOpcodeHands() local
2872 assert(LogicOpcode == TargetOpcode::G_AND || in matchHoistLogicOpWithSameOpcodeHands()
2873 LogicOpcode == TargetOpcode::G_OR || in matchHoistLogicOpWithSameOpcodeHands()
2874 LogicOpcode == TargetOpcode::G_XOR); in matchHoistLogicOpWithSameOpcodeHands()
2904 if (!isLegalOrBeforeLegalizer({LogicOpcode, {XTy, YTy}})) in matchHoistLogicOpWithSameOpcodeHands()
2939 InstructionBuildSteps LogicSteps(LogicOpcode, LogicBuildSteps); in matchHoistLogicOpWithSameOpcodeHands()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp4786 unsigned LogicOpcode = N->getOpcode(); in hoistLogicOpWithSameOpcodeHands() local
4788 assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || in hoistLogicOpWithSameOpcodeHands()
4789 LogicOpcode == ISD::XOR) && "Expected logic opcode"); in hoistLogicOpWithSameOpcodeHands()
4816 !TLI.isOperationLegalOrCustom(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
4821 !TLI.isTypeDesirableForOp(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
4824 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
4838 if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
4846 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
4858 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
4867 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
[all …]
H A DTargetLowering.cpp3473 unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR; in simplifySetCCWithCTPOP() local
3474 return DAG.getNode(LogicOpcode, dl, VT, LHS, RHS); in simplifySetCCWithCTPOP()