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Searched refs:LoadVT (Results 1 – 16 of 16) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp4563 static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT, in adjustLoadValueTypeImpl() argument
4566 if (!LoadVT.isVector()) in adjustLoadValueTypeImpl()
4572 EVT FittingLoadVT = LoadVT; in adjustLoadValueTypeImpl()
4573 if ((LoadVT.getVectorNumElements() % 2) == 1) { in adjustLoadValueTypeImpl()
4575 EVT::getVectorVT(*DAG.getContext(), LoadVT.getVectorElementType(), in adjustLoadValueTypeImpl()
4576 LoadVT.getVectorNumElements() + 1); in adjustLoadValueTypeImpl()
4591 if ((LoadVT.getVectorNumElements() % 2) == 1) in adjustLoadValueTypeImpl()
4612 EVT LoadVT = M->getValueType(0); in adjustLoadValueType() local
4614 EVT EquivLoadVT = LoadVT; in adjustLoadValueType()
4615 if (LoadVT.isVector()) { in adjustLoadValueType()
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H A DSIISelLowering.h240 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetLowering.h541 virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, in isLoadBitCastBeneficial() argument
546 if (!LoadVT.isSimple() || !BitcastVT.isSimple()) in isLoadBitCastBeneficial()
549 MVT LoadMVT = LoadVT.getSimpleVT(); in isLoadBitCastBeneficial()
2537 EVT LoadVT = getValueType(DL, Load->getType()); in isExtLoad() local
2541 if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) && in isExtLoad()
2554 return isLoadExtLegal(LType, VT, LoadVT); in isExtLoad()
H A DBasicTTIImpl.h903 EVT LoadVT = EVT::getEVT(Src);
907 TLI->isLoadExtLegal(LType, ExtVT, LoadVT))
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DStatepointLowering.cpp1235 auto LoadVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitGCRelocate() local
1239 DAG.getLoad(LoadVT, getCurSDLoc(), Chain, SpillSlot, LoadMMO); in visitGCRelocate()
H A DSelectionDAGBuilder.cpp7511 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, in getMemCmpLoad() argument
7518 Type::getIntNTy(PtrVal->getContext(), LoadVT.getScalarSizeInBits()); in getMemCmpLoad()
7519 if (LoadVT.isVector()) in getMemCmpLoad()
7520 LoadTy = FixedVectorType::get(LoadTy, LoadVT.getVectorNumElements()); in getMemCmpLoad()
7546 Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, Ptr, in getMemCmpLoad()
7624 MVT LoadVT; in visitMemCmpBCmpCall() local
7630 LoadVT = MVT::i16; in visitMemCmpBCmpCall()
7633 LoadVT = MVT::i32; in visitMemCmpBCmpCall()
7638 LoadVT = hasFastLoadsAndCompare(NumBitsToCompare); in visitMemCmpBCmpCall()
7642 if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE) in visitMemCmpBCmpCall()
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H A DLegalizeDAG.cpp880 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT()); in LegalizeLoadOps() local
882 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) { in LegalizeLoadOps()
886 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType; in LegalizeLoadOps()
888 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr, in LegalizeLoadOps()
H A DTargetLowering.cpp7317 EVT LoadVT = EVT::getIntegerVT(*DAG.getContext(), NumLoadBits); in scalarizeVectorLoad() local
7324 APInt::getLowBitsSet(NumLoadBits, SrcEltBits), SL, LoadVT); in scalarizeVectorLoad()
7329 DAG.getExtLoad(ISD::EXTLOAD, SL, LoadVT, Chain, BasePTR, in scalarizeVectorLoad()
7339 LoadVT, SL, /*LegalTypes=*/false); in scalarizeVectorLoad()
7340 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount); in scalarizeVectorLoad()
7342 DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask); in scalarizeVectorLoad()
H A DDAGCombiner.cpp5615 EVT LoadVT = MLoad->getMemoryVT(); in visitAND() local
5617 if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT, LoadVT)) { in visitAND()
5623 LoadVT.getVectorElementType().getScalarSizeInBits(); in visitAND()
5628 LoadVT, MLoad->getMemOperand(), MLoad->getAddressingMode(), in visitAND()
16895 EVT LoadVT; in getStoreMergeCandidates() local
16899 LoadVT = Ld->getMemoryVT(); in getStoreMergeCandidates()
16901 if (MemVT != LoadVT) in getStoreMergeCandidates()
16933 if (LoadVT != OtherLd->getMemoryVT()) in getStoreMergeCandidates()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2558 EVT LoadVT = EltVT; in LowerFormalArguments() local
2560 LoadVT = MVT::i8; in LowerFormalArguments()
2565 LoadVT = MVT::i32; in LowerFormalArguments()
2567 EVT VecVT = EVT::getVectorVT(F->getContext(), LoadVT, NumElts); in LowerFormalArguments()
2581 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P, in LowerFormalArguments()
2593 LoadVT.getFixedSizeInBits()) { in LowerFormalArguments()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.h1329 bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
H A DX86ISelLowering.cpp5380 bool X86TargetLowering::isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, in isLoadBitCastBeneficial() argument
5383 if (!Subtarget.hasAVX512() && !LoadVT.isVector() && BitcastVT.isVector() && in isLoadBitCastBeneficial()
5387 if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1 && LoadVT == MVT::i8) in isLoadBitCastBeneficial()
5391 if (LoadVT.isVector() && BitcastVT.isVector() && in isLoadBitCastBeneficial()
5392 isTypeLegal(LoadVT) && isTypeLegal(BitcastVT)) in isLoadBitCastBeneficial()
5395 return TargetLowering::isLoadBitCastBeneficial(LoadVT, BitcastVT, DAG, MMO); in isLoadBitCastBeneficial()
40009 MVT LoadVT = VT.isFloatingPoint() ? MVT::getFloatingPointVT(SrcVTSize) in combineBitcast() local
40011 LoadVT = MVT::getVectorVT(LoadVT, SrcVT.getVectorNumElements()); in combineBitcast()
40013 SDVTList Tys = DAG.getVTList(LoadVT, MVT::Other); in combineBitcast()
47466 MVT LoadVT = MVT::getVectorVT(MemVT, 128 / NumBits); in combineX86INT_TO_FP() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp6378 EVT LoadVT = N->getValueType(0); in combineBSWAP() local
6379 if (LoadVT == MVT::i16) in combineBSWAP()
6380 LoadVT = MVT::i32; in combineBSWAP()
6383 DAG.getVTList(LoadVT, MVT::Other), in combineBSWAP()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp14270 EVT LoadVT = VT; in performLDNT1Combine() local
14272 LoadVT = VT.changeTypeToInteger(); in performLDNT1Combine()
14275 SDValue PassThru = DAG.getConstant(0, DL, LoadVT); in performLDNT1Combine()
14276 SDValue L = DAG.getMaskedLoad(LoadVT, DL, MINode->getChain(), in performLDNT1Combine()
14301 EVT LoadVT = VT; in performLD1ReplicateCombine() local
14303 LoadVT = VT.changeTypeToInteger(); in performLD1ReplicateCombine()
14306 SDValue Load = DAG.getNode(Opcode, DL, {LoadVT, MVT::Other}, Ops); in performLD1ReplicateCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp14819 MVT LoadVT = VT.getSimpleVT(); in PerformDAGCombine() local
14821 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 || in PerformDAGCombine()
14822 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32)) in PerformDAGCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp14801 EVT LoadVT = isLaneOp ? VecTy.getVectorElementType() : AlignedVecTy; in CombineBaseUpdate() local
14802 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, dl, SDTys, Ops, LoadVT, in CombineBaseUpdate()