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Searched refs:LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT (Results 1 – 9 of 9) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7601 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x00000019 macro
H A Ddce_8_0_sh_mask.h3200 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 macro
H A Ddce_10_0_sh_mask.h3122 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 macro
H A Ddce_11_0_sh_mask.h3192 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 macro
H A Ddce_11_2_sh_mask.h3440 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 macro
H A Ddce_12_0_sh_mask.h9257 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT … macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_sh_mask.h43240 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT … macro
H A Ddcn_1_0_sh_mask.h40006 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h48749 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT … macro