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Searched refs:LLT (Results 1 – 25 of 150) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86LegalizerInfo.cpp75 .minScalar(0, LLT::scalar(32)) in X86LegalizerInfo()
102 const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0)); in setLegalizerInfo32bit()
103 const LLT s1 = LLT::scalar(1); in setLegalizerInfo32bit()
104 const LLT s8 = LLT::scalar(8); in setLegalizerInfo32bit()
105 const LLT s16 = LLT::scalar(16); in setLegalizerInfo32bit()
106 const LLT s32 = LLT::scalar(32); in setLegalizerInfo32bit()
107 const LLT s64 = LLT::scalar(64); in setLegalizerInfo32bit()
108 const LLT s128 = LLT::scalar(128); in setLegalizerInfo32bit()
197 const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0)); in setLegalizerInfo64bit()
198 const LLT s1 = LLT::scalar(1); in setLegalizerInfo64bit()
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H A DX86InstructionSelector.cpp74 unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
128 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
129 const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
170 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass()
198 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg, in getRegClass()
395 unsigned X86InstructionSelector::getLoadStoreOp(const LLT &Ty, in getLoadStoreOp()
404 if (Ty == LLT::scalar(8)) { in getLoadStoreOp()
407 } else if (Ty == LLT::scalar(16)) { in getLoadStoreOp()
410 } else if (Ty == LLT::scalar(32) || Ty == LLT::pointer(0, 32)) { in getLoadStoreOp()
420 } else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64)) { in getLoadStoreOp()
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H A DX86RegisterBankInfo.cpp45 LLT) const { in getRegBankFromRegClass()
66 X86GenRegisterBankInfo::getPartialMappingIdx(const LLT &Ty, bool isFP) { in getPartialMappingIdx()
151 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getSameOperandsMapping()
189 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
215 const LLT Ty0 = MRI.getType(Op0.getReg()); in getInstrMapping()
216 const LLT Ty1 = MRI.getType(Op1.getReg()); in getInstrMapping()
225 LLT Ty1 = MRI.getType(MI.getOperand(2).getReg()); in getInstrMapping()
226 LLT Ty2 = MRI.getType(MI.getOperand(3).getReg()); in getInstrMapping()
244 const LLT Ty0 = MRI.getType(Op0.getReg()); in getInstrMapping()
245 const LLT Ty1 = MRI.getType(Op1.getReg()); in getInstrMapping()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizerHelper.h88 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
93 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
96 LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
100 LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
105 LLT NarrowTy);
110 LLT MoreTy);
123 void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
129 void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
134 void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx = 0,
140 void narrowScalarDst(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx,
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H A DLegalizerInfo.h109 LLT Type;
111 InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Type(Type) {} in InstrAspect()
112 InstrAspect(unsigned Opcode, unsigned Idx, LLT Type) in InstrAspect()
126 ArrayRef<LLT> Types;
138 constexpr LegalityQuery(unsigned Opcode, const ArrayRef<LLT> Types, in LegalityQuery()
141 constexpr LegalityQuery(unsigned Opcode, const ArrayRef<LLT> Types) in LegalityQuery()
156 LLT NewType;
159 const LLT NewType) in LegalizeActionStep()
170 std::function<std::pair<unsigned, LLT>(const LegalityQuery &)>;
174 LLT Type0;
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H A DLegalizationArtifactCombiner.h86 const LLT DstTy = MRI.getType(DstReg); in tryCombineAnyExt()
115 LLT DstTy = MRI.getType(DstReg); in tryCombineZExt()
120 LLT SrcTy = MRI.getType(SrcReg); in tryCombineZExt()
146 const LLT DstTy = MRI.getType(DstReg); in tryCombineZExt()
171 LLT DstTy = MRI.getType(DstReg); in tryCombineSExt()
175 LLT SrcTy = MRI.getType(SrcReg); in tryCombineSExt()
201 const LLT DstTy = MRI.getType(DstReg); in tryCombineSExt()
228 const LLT DstTy = MRI.getType(DstReg); in tryCombineTrunc()
243 const LLT MergeSrcTy = MRI.getType(MergeSrcReg); in tryCombineTrunc()
244 const LLT DstTy = MRI.getType(DstReg); in tryCombineTrunc()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DLowLevelTypeImpl.h40 class LLT {
43 static LLT scalar(unsigned SizeInBits) { in scalar()
45 return LLT{/*isPointer=*/false, /*isVector=*/false, /*NumElements=*/0, in scalar()
50 static LLT pointer(unsigned AddressSpace, unsigned SizeInBits) { in pointer()
52 return LLT{/*isPointer=*/true, /*isVector=*/false, /*NumElements=*/0, in pointer()
58 static LLT vector(uint16_t NumElements, unsigned ScalarSizeInBits) { in vector()
61 return LLT{/*isPointer=*/false, /*isVector=*/true, NumElements, in vector()
66 static LLT vector(uint16_t NumElements, LLT ScalarTy) { in vector()
69 return LLT{ScalarTy.isPointer(), /*isVector=*/true, NumElements, in vector()
74 static LLT scalarOrVector(uint16_t NumElements, LLT ScalarTy) { in scalarOrVector()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Support/
H A DLowLevelType.cpp18 LLT::LLT(MVT VT) { in LLT() function in LLT
36 void LLT::print(raw_ostream &OS) const { in print()
48 const constexpr LLT::BitFieldInfo LLT::ScalarSizeFieldInfo;
49 const constexpr LLT::BitFieldInfo LLT::PointerSizeFieldInfo;
50 const constexpr LLT::BitFieldInfo LLT::PointerAddressSpaceFieldInfo;
51 const constexpr LLT::BitFieldInfo LLT::VectorElementsFieldInfo;
52 const constexpr LLT::BitFieldInfo LLT::VectorSizeFieldInfo;
53 const constexpr LLT::BitFieldInfo LLT::PointerVectorElementsFieldInfo;
54 const constexpr LLT::BitFieldInfo LLT::PointerVectorSizeFieldInfo;
55 const constexpr LLT::BitFieldInfo LLT::PointerVectorAddressSpaceFieldInfo;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp49 static LLT getPow2VectorType(LLT Ty) { in getPow2VectorType()
56 static LLT getPow2ScalarType(LLT Ty) { in getPow2ScalarType()
59 return LLT::scalar(Pow2Bits); in getPow2ScalarType()
67 const LLT Ty = Query.Types[TypeIdx]; in isSmallOddVector()
71 const LLT EltTy = Ty.getElementType(); in isSmallOddVector()
81 const LLT Ty = Query.Types[TypeIdx]; in sizeIsMultipleOf32()
88 const LLT Ty = Query.Types[TypeIdx]; in isWideVec16()
89 const LLT EltTy = Ty.getScalarType(); in isWideVec16()
96 const LLT Ty = Query.Types[TypeIdx]; in oneMoreElement()
97 const LLT EltTy = Ty.getElementType(); in oneMoreElement()
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H A DAMDGPUArgumentUsageInfo.cpp88 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
95 &AMDGPU::SGPR_128RegClass, LLT::vector(4, 32)); in getPreloadedValue()
100 LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64)); in getPreloadedValue()
103 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
106 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
109 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
113 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
117 LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64)); in getPreloadedValue()
121 LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64)); in getPreloadedValue()
124 &AMDGPU::SGPR_64RegClass, LLT::scalar(64)); in getPreloadedValue()
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H A DAMDGPURegisterBankInfo.cpp126 const LLT S32 = LLT::scalar(32); in applyBank()
127 assert(MRI.getType(SrcReg) == LLT::scalar(1)); in applyBank()
165 if (MRI.getType(Reg) == LLT::scalar(1)) { in applyBank()
277 LLT Ty) const { in getRegBankFromRegClass()
290 return Ty == LLT::scalar(1) ? AMDGPU::VCCRegBank : AMDGPU::SGPRRegBank; in getRegBankFromRegClass()
541 LLT PtrTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrAlternativeMappings()
648 LLT HalfTy, in split64BitValueForMapping()
669 LLT NewTy) { in setRegsToType()
676 static LLT getHalfSizedType(LLT Ty) { in getHalfSizedType()
679 return LLT::scalarOrVector(Ty.getNumElements() / 2, Ty.getElementType()); in getHalfSizedType()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp41 const LLT p0 = LLT::pointer(0, 64); in AArch64LegalizerInfo()
42 const LLT s1 = LLT::scalar(1); in AArch64LegalizerInfo()
43 const LLT s8 = LLT::scalar(8); in AArch64LegalizerInfo()
44 const LLT s16 = LLT::scalar(16); in AArch64LegalizerInfo()
45 const LLT s32 = LLT::scalar(32); in AArch64LegalizerInfo()
46 const LLT s64 = LLT::scalar(64); in AArch64LegalizerInfo()
47 const LLT s128 = LLT::scalar(128); in AArch64LegalizerInfo()
48 const LLT s256 = LLT::scalar(256); in AArch64LegalizerInfo()
49 const LLT s512 = LLT::scalar(512); in AArch64LegalizerInfo()
50 const LLT v16s8 = LLT::vector(16, 8); in AArch64LegalizerInfo()
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H A DAArch64InstructionSelector.cpp164 bool tryOptConstantBuildVec(MachineInstr &MI, LLT DstTy,
263 const RegisterBank &DstRB, LLT ScalarTy,
483 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, in getRegClassForTypeOnBank()
622 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in unsupportedBinOp()
965 static unsigned selectFPConvOpc(unsigned GenericOpc, LLT DstTy, LLT SrcTy) { in selectFPConvOpc()
1049 LLT Ty = MRI.getType(True); in emitSelect()
1373 LLT Ty = MRI.getType(TestReg); in emitTestBit()
1610 MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1); in selectCompareBranch()
1631 static Optional<int64_t> getVectorSHLImm(LLT SrcTy, Register Reg, MachineRegisterInfo &MRI) { in getVectorSHLImm()
1667 const LLT Ty = MRI.getType(DstReg); in selectVectorSHL()
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H A DAArch64PostLegalizerCombiner.cpp52 std::tuple<unsigned, LLT, Register> &MatchInfo) { in matchExtractVecEltPairwiseAdd() argument
55 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in matchExtractVecEltPairwiseAdd()
95 std::tuple<unsigned, LLT, Register> &MatchInfo) { in applyExtractVecEltPairwiseAdd() argument
99 LLT Ty = std::get<1>(MatchInfo); in applyExtractVecEltPairwiseAdd()
101 LLT s64 = LLT::scalar(64); in applyExtractVecEltPairwiseAdd()
128 const LLT Ty = MRI.getType(LHS); in matchAArch64MulConstCombine()
211 auto Shift = B.buildConstant(LLT::scalar(64), ShiftAmt); in matchAArch64MulConstCombine()
226 B.buildShl(DstReg, Res, B.buildConstant(LLT::scalar(64), TrailingZeroes)); in matchAArch64MulConstCombine()
251 LLT Ty = MRI.getType(Src); in matchBitfieldExtractFromSExtInReg()
252 assert((Ty == LLT::scalar(32) || Ty == LLT::scalar(64)) && in matchBitfieldExtractFromSExtInReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DLegalityPredicates.cpp28 LegalityPredicate LegalityPredicates::typeIs(unsigned TypeIdx, LLT Type) { in typeIs()
35 std::initializer_list<LLT> TypesInit) { in typeInSet()
36 SmallVector<LLT, 4> Types = TypesInit; in typeInSet()
44 std::initializer_list<std::pair<LLT, LLT>> TypesInit) { in typePairInSet() argument
45 SmallVector<std::pair<LLT, LLT>, 4> Types = TypesInit; in typePairInSet()
47 std::pair<LLT, LLT> Match = {Query.Types[TypeIdx0], Query.Types[TypeIdx1]}; in typePairInSet()
88 LLT Ty = Query.Types[TypeIdx]; in isPointer()
94 LLT EltTy) { in elementTypeIs()
96 const LLT QueryTy = Query.Types[TypeIdx]; in elementTypeIs()
104 const LLT QueryTy = Query.Types[TypeIdx]; in scalarNarrowerThan()
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H A DLegalizerHelper.cpp44 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) { in getNarrowTypeBreakDown()
60 LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize); in getNarrowTypeBreakDown()
62 LeftoverTy = LLT::scalar(LeftoverSize); in getNarrowTypeBreakDown()
69 static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) { in getFloatTypeForLLT()
147 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts, in extractParts()
154 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, in extractParts()
155 LLT MainTy, LLT &LeftoverTy, in extractParts()
177 LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize); in extractParts()
179 LeftoverTy = LLT::scalar(LeftoverSize); in extractParts()
200 LLT ResultTy, LLT PartTy, in insertParts()
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H A DLegalizeMutations.cpp17 LegalizeMutation LegalizeMutations::changeTo(unsigned TypeIdx, LLT Ty) { in changeTo()
32 const LLT OldTy = Query.Types[TypeIdx]; in changeElementTo()
33 const LLT NewTy = Query.Types[FromTypeIdx]; in changeElementTo()
39 LLT NewEltTy) { in changeElementTo()
41 const LLT OldTy = Query.Types[TypeIdx]; in changeElementTo()
49 const LLT OldTy = Query.Types[TypeIdx]; in changeElementSizeTo()
50 const LLT NewTy = Query.Types[FromTypeIdx]; in changeElementSizeTo()
51 const LLT NewEltTy = LLT::scalar(NewTy.getScalarSizeInBits()); in changeElementSizeTo()
59 const LLT Ty = Query.Types[TypeIdx]; in widenScalarOrEltToNextPow2()
69 const LLT VecTy = Query.Types[TypeIdx]; in moreElementsToNextPow2()
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H A DMachineIRBuilder.cpp159 MachineInstrBuilder MachineIRBuilder::buildJumpTable(const LLT PtrTy, in buildJumpTable()
165 void MachineIRBuilder::validateUnaryOp(const LLT Res, const LLT Op0) { in validateUnaryOp()
170 void MachineIRBuilder::validateBinaryOp(const LLT Res, const LLT Op0, in validateBinaryOp()
171 const LLT Op1) { in validateBinaryOp()
176 void MachineIRBuilder::validateShiftOp(const LLT Res, const LLT Op0, in validateShiftOp()
177 const LLT Op1) { in validateShiftOp()
194 const LLT ValueTy, uint64_t Value) { in materializePtrAdd()
211 LLT PtrTy = Res.getLLTTy(*getMRI()); in buildMaskLowPtrBits()
212 LLT MaskTy = LLT::scalar(PtrTy.getSizeInBits()); in buildMaskLowPtrBits()
257 LLT Ty = Res.getLLTTy(*getMRI()); in buildConstant()
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H A DCallLowering.cpp246 SmallVector<LLT, 8> LLTs; in unpackRegs()
260 LLT LLTy = MRI.getType(DstRegs[0]); in mergeVectorRegsToResultRegs()
261 LLT PartLLT = MRI.getType(SrcRegs[0]); in mergeVectorRegsToResultRegs()
264 LLT LCMTy = getLCMType(LLTy, PartLLT); in mergeVectorRegsToResultRegs()
314 ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, in buildCopyFromRegs()
340 LLT LocTy = MRI.getType(SrcReg); in buildCopyFromRegs()
356 LLT OrigTy = MRI.getType(OrigRegs[0]); in buildCopyFromRegs()
362 auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs); in buildCopyFromRegs()
379 LLT NewTy = PartLLT.changeElementType(LLTy.getElementType()) in buildCopyFromRegs()
389 LLT GCDTy = getGCDType(LLTy, PartLLT); in buildCopyFromRegs()
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H A DLegalizerInfo.cpp106 const std::pair<unsigned, LLT> &Mutation) { in hasNoSimpleLoops()
123 std::pair<unsigned, LLT> Mutation) { in mutationIsSane()
130 const LLT OldTy = Q.Types[TypeIdx]; in mutationIsSane()
131 const LLT NewTy = Mutation.second; in mutationIsSane()
195 return {LegalizeAction::UseLegacyRules, 0, LLT{}}; in apply()
200 std::pair<unsigned, LLT> Mutation = Rule.determineMutation(Query); in apply()
211 return {LegalizeAction::Unsupported, 0, LLT{}}; in apply()
310 const LLT Type = LLT2Action.first; in computeTables()
388 std::pair<LegalizeAction, LLT>
400 static LLT getTypeFromTypeIdx(const MachineInstr &MI, in getTypeFromTypeIdx()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DLowLevelType.cpp21 LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL) { in getLLTForType()
24 LLT ScalarTy = getLLTForType(*VTy->getElementType(), DL); in getLLTForType()
27 return LLT::vector(NumElements, ScalarTy); in getLLTForType()
32 return LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace)); in getLLTForType()
40 return LLT::scalar(SizeInBits); in getLLTForType()
43 return LLT(); in getLLTForType()
46 MVT llvm::getMVTForLLT(LLT Ty) { in getMVTForLLT()
55 LLT llvm::getLLTForMVT(MVT Ty) { in getLLTForMVT()
57 return LLT::scalar(Ty.getSizeInBits()); in getLLTForMVT()
59 return LLT::vector(Ty.getVectorNumElements(), in getLLTForMVT()
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/netbsd-src/libexec/ftpd/
H A Dextern.h95 # define LLT long macro
105 # define LLT long long macro
275 LLT limit; /* Max connections (-1 = unlimited) */
277 LLT maxfilesize; /* Maximum file size of uploads */
278 LLT maxrateget; /* Maximum get transfer rate throttle */
279 LLT maxrateput; /* Maximum put transfer rate throttle */
280 LLT maxtimeout; /* Maximum permitted timeout */
283 LLT portmin; /* Minimum port for passive mode */
284 LLT portmax; /* Maximum port for passive mode */
285 LLT rateget; /* Get (RETR) transfer rate throttle */
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp179 LLT) const { in getRegBankFromRegClass()
239 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
274 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
284 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
297 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
304 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
318 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
319 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
327 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
328 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp21 LLT ValTy;
22 LLT PtrTy;
62 std::initializer_list<LLT> SupportedValues) { in CheckTyN()
69 const LLT s1 = LLT::scalar(1); in MipsLegalizerInfo()
70 const LLT s32 = LLT::scalar(32); in MipsLegalizerInfo()
71 const LLT s64 = LLT::scalar(64); in MipsLegalizerInfo()
72 const LLT v16s8 = LLT::vector(16, 8); in MipsLegalizerInfo()
73 const LLT v8s16 = LLT::vector(8, 16); in MipsLegalizerInfo()
74 const LLT v4s32 = LLT::vector(4, 32); in MipsLegalizerInfo()
75 const LLT v2s64 = LLT::vector(2, 64); in MipsLegalizerInfo()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DLowLevelType.h29 LLT getLLTForType(Type &Ty, const DataLayout &DL);
33 MVT getMVTForLLT(LLT Ty);
37 LLT getLLTForMVT(MVT Ty);
41 const llvm::fltSemantics &getFltSemanticForLLT(LLT Ty);

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