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Searched refs:LEVEL0_MPLL_FB_DIV_MASK (Results 1 – 2 of 2) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Drv6xxd.h84 # define LEVEL0_MPLL_FB_DIV_MASK (0xfff << 8) macro
H A Dradeon_rv6xx_dpm.c395 ~LEVEL0_MPLL_FB_DIV_MASK); in rv6xx_memory_clock_entry_set_feedback_divider()