/netbsd-src/sys/external/bsd/compiler_rt/dist/lib/xray/ |
H A D | xray_trampoline_AArch64.S | 43 LDP Q6, Q7, [SP], #32 44 LDP Q4, Q5, [SP], #32 45 LDP Q2, Q3, [SP], #32 46 LDP Q0, Q1, [SP], #32 47 LDP X7, X30, [SP], #16 48 LDP X5, X6, [SP], #16 49 LDP X3, X4, [SP], #16 50 LDP X1, X2, [SP], #16 87 LDP X7, X30, [SP], #16 88 LDP X5, X6, [SP], #16 [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
H A D | LoopDataPrefetch.cpp | 179 LoopDataPrefetch LDP(AC, DT, LI, SE, TTI, ORE); in run() local 180 bool Changed = LDP.run(); in run() 206 LoopDataPrefetch LDP(AC, DT, LI, SE, TTI, ORE); in runOnFunction() local 207 return LDP.run(); in runOnFunction()
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/netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/ |
H A D | cortex-a53.md | 135 ;; This is most obvious for LDRD from AArch32 and LDP (X register) from 136 ;; AArch64, both are tagged load2 but LDP will load 128-bits compared to 154 ;; Model AArch64-sized LDP Xm, Xn, [Xa]
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/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/ |
H A D | cortex-a53.md | 135 ;; This is most obvious for LDRD from AArch32 and LDP (X register) from 136 ;; AArch64, both are tagged load2 but LDP will load 128-bits compared to 154 ;; Model AArch64-sized LDP Xm, Xn, [Xa]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64Schedule.td | 61 // LDP,LDPSW,LDNP,LDXP,LDAXP
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H A D | AArch64FalkorHWPFFix.cpp | 133 FalkorMarkStridedAccesses LDP(LI, SE); in runOnFunction() local 134 return LDP.run(); in runOnFunction()
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H A D | AArch64SchedTSV110.td | 427 def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi], (instregex "^LDP(W|X)i$")>; 428 def : InstRW<[TSV110Wr_4cyc_1LdSt_1ALUAB, WriteLDHi, WriteAdr],(instregex "^LDP(W|X)(post|pre)$")>; 503 def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteLDHi, WriteAdr], (instregex "^LDP[DQS](post|pre)")>;
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H A D | AArch64SchedFalkorDetails.td | 1106 (instregex "LDP(D|S)i$")>; 1108 (instregex "LDP(D|S)(pre|post)$")>; 1170 (instregex "^LDP(W|X)i$")>; 1172 (instregex "^LDP(W|X)(post|pre)$")>;
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H A D | AArch64SchedExynosM4.td | 613 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 694 WriteAdr], (instregex "^LDP[SD]post")>; 700 WriteAdr], (instregex "^LDP[SD]pre")>;
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H A D | AArch64SchedExynosM3.td | 516 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 579 WriteAdr], (instregex "^LDP[DS](post|pre)")>;
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H A D | AArch64SchedA55.td | 228 def : InstRW<[CortexA55WriteVLD2,CortexA55WriteVLD1], (instregex "LDP.*")>;
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H A D | AArch64SchedExynosM5.td | 670 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 750 WriteAdr], (instregex "^LDP[SD](post|pre)")>;
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H A D | AArch64ISelLowering.h | 441 LDP, enumerator
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H A D | AArch64SchedThunderX3T110.td | 323 // Load vector pair, immed offset, Q-form [LDP/LDNP]. 333 // Load vector pair, immed offset, S/D-form [LDP/LDNP]. 870 // LDP only breaks into *one* LS micro-op. Thus
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H A D | AArch64SchedCyclone.td | 268 // LDP high register write is fused with the load, but a nop micro-op remains.
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H A D | AArch64SchedKryoDetails.td | 1420 (instregex "LDP(D|S)(post|pre)")>; 1432 (instregex "LDP(W|X)(post|pre)")>;
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H A D | AArch64SchedThunderX2T99.td | 610 // LDP only breaks into *one* LS micro-op. Thus
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/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
H A D | omap3-ldp.dts | 12 model = "TI OMAP3430 LDP (Zoom1 Labrador)";
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/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/aarch64/ |
H A D | thunderx3t110.md | 538 ; the LDP/LDNP imm-offset S/D/Q suppplies the first arg with latency 4 541 ; other LDP ones do.
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H A D | constraints.md | 269 ;; Used for storing or loading pairs in an AdvSIMD register using an STP/LDP
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/netbsd-src/external/gpl3/gcc/dist/gcc/config/aarch64/ |
H A D | thunderx3t110.md | 538 ; the LDP/LDNP imm-offset S/D/Q suppplies the first arg with latency 4 541 ; other LDP ones do.
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H A D | constraints.md | 277 ;; Used for storing or loading pairs in an AdvSIMD register using an STP/LDP
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/netbsd-src/sys/external/bsd/sljit/dist/sljit_src/ |
H A D | sljitNativeARM_64.c | 95 #define LDP 0xa9400000 macro 1216 FAIL_IF(push_inst(compiler, LDP | RT(prev) | RT2(i) | RN(TMP_SP) | offs)); in sljit_emit_return() 1231 FAIL_IF(push_inst(compiler, LDP | RT(prev) | RT2(i) | RN(TMP_SP) | offs)); in sljit_emit_return()
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/netbsd-src/external/bsd/ipf/dist/etc/ |
H A D | services | 666 ldp 646/tcp # LDP 667 ldp 646/udp # LDP
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/netbsd-src/external/lgpl3/mpfr/dist/ |
H A D | configure.ac | 69 dnl https://tldp.org/LDP/abs/html/exitcodes.html suggests the range 64-113
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