| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 203 bool WantResult = true, bool IsZExt = false);
221 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
222 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
235 bool IsZExt = false);
239 bool IsZExt = false);
257 bool IsZExt = true);
260 bool IsZExt = true);
263 bool IsZExt = false);
303 bool IsZExt = isa<ZExtInst>(I); in isIntExtFree() local
310 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) in isIntExtFree()
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| H A D | AArch64ISelLowering.cpp | 3441 Entry.IsZExt = false; in LowerFSINCOS()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetCallingConv.h | 29 unsigned IsZExt : 1; ///< Zero extended
62 : IsZExt(0), IsSExt(0), IsInReg(0), IsSRet(0), IsByVal(0), IsByRef(0), in ArgFlagsTy()
73 bool isZExt() const { return IsZExt; } in isZExt()
74 void setZExt() { IsZExt = 1; } in setZExt()
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| H A D | MachineFrameInfo.h | 506 void setObjectZExt(int ObjectIdx, bool IsZExt) { in setObjectZExt() argument
509 Objects[ObjectIdx+NumFixedObjects].isZExt = IsZExt; in setObjectZExt()
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| H A D | TargetLowering.h | 279 bool IsZExt : 1; variable
297 : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false), in ArgListEntry()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 162 const TargetRegisterClass *RC, bool IsZExt = true,
169 unsigned DestReg, bool IsZExt);
452 bool IsZExt, unsigned FP64LoadOpc) { in PPCEmitLoad() argument
481 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8) in PPCEmitLoad()
485 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8) in PPCEmitLoad()
819 bool IsZExt, unsigned DestReg, in PPCEmitCmp() argument
844 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue(); in PPCEmitCmp()
845 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) in PPCEmitCmp()
918 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; in PPCEmitCmp()
920 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; in PPCEmitCmp()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 190 bool IsZExt);
1757 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet() local
1758 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
1895 unsigned DestReg, bool IsZExt) { in emitIntExt() argument
1903 if (IsZExt) in emitIntExt()
1982 bool IsZExt = Opcode == Instruction::LShr; in selectShift() local
1983 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt)) in selectShift()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | BasicAliasAnalysis.cpp | 1160 bool IsZExt = DecompGEP1.VarIndices[i].ZExtBits > 0 || isa<ZExtInst>(V); in aliasGEP() local
1161 SignKnownZero |= IsZExt; in aliasGEP()
1162 SignKnownOne &= !IsZExt; in aliasGEP()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1989 Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned); in ExpandLibCall()
2160 Entry.IsZExt = !isSigned; in ExpandDivRemLibCall()
2169 Entry.IsZExt = !isSigned; in ExpandDivRemLibCall()
2254 Entry.IsZExt = false; in ExpandSinCosLibCall()
2262 Entry.IsZExt = false; in ExpandSinCosLibCall()
2270 Entry.IsZExt = false; in ExpandSinCosLibCall()
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| H A D | FastISel.cpp | 1041 if (Arg.IsZExt) in lowerCallTo()
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| H A D | SelectionDAGBuilder.cpp | 9403 Entry.IsZExt = false; in LowerCallTo()
9504 if (Args[i].IsZExt) in LowerCallTo()
9586 else if (Args[i].IsZExt) in LowerCallTo()
9610 CLI.RetZExt == Args[i].IsZExt)) in LowerCallTo()
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| H A D | LegalizeIntegerTypes.cpp | 4017 Entry.IsZExt = false; in ExpandIntRes_XMULO()
4025 Entry.IsZExt = false; in ExpandIntRes_XMULO()
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| H A D | TargetLowering.cpp | 112 IsZExt = Attrs.hasParamAttribute(ArgIdx, Attribute::ZExt); in setAttributes()
166 Entry.IsZExt = !Entry.IsSExt; in makeLibCall()
170 Entry.IsSExt = Entry.IsZExt = false; in makeLibCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 449 Entry.IsZExt = !IsSigned; in LowerDivRem()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9318 Entry.IsZExt = false; in LowerFSINCOS()
9328 Entry.IsZExt = false; in LowerFSINCOS()
18707 Entry.IsZExt = !isSigned; in getDivRemArgList()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 27928 Entry.IsZExt = false; in LowerWin64_i128OP()
29889 Entry.IsZExt = false; in LowerFSINCOS()
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