| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Instrumentation/ |
| H A D | MemProfiler.cpp | 150 bool IsWrite; member
174 Value *Addr, uint32_t TypeSize, bool IsWrite);
178 bool IsWrite);
336 Access.IsWrite = false; in isInterestingMemoryAccess()
343 Access.IsWrite = true; in isInterestingMemoryAccess()
351 Access.IsWrite = true; in isInterestingMemoryAccess()
359 Access.IsWrite = true; in isInterestingMemoryAccess()
374 Access.IsWrite = true; in isInterestingMemoryAccess()
378 Access.IsWrite = false; in isInterestingMemoryAccess()
416 uint32_t TypeSize, bool IsWrite) { in instrumentMaskedLoadOrStore() argument
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| H A D | ThreadSanitizer.cpp | 450 const bool IsWrite = isa<StoreInst>(*I); in chooseInstructionsToInstrument() local
451 Value *Addr = IsWrite ? cast<StoreInst>(I)->getPointerOperand() in chooseInstructionsToInstrument()
457 if (!IsWrite) { in chooseInstructionsToInstrument()
492 if (IsWrite) { in chooseInstructionsToInstrument()
614 const bool IsWrite = isa<StoreInst>(*II.Inst); in instrumentLoadOrStore() local
615 Value *Addr = IsWrite ? cast<StoreInst>(II.Inst)->getPointerOperand() in instrumentLoadOrStore()
627 if (IsWrite && isVtableAccess(II.Inst)) { in instrumentLoadOrStore()
645 if (!IsWrite && isVtableAccess(II.Inst)) { in instrumentLoadOrStore()
652 const unsigned Alignment = IsWrite ? cast<StoreInst>(II.Inst)->getAlignment() in instrumentLoadOrStore()
657 (IsWrite ? cast<StoreInst>(II.Inst)->isVolatile() in instrumentLoadOrStore()
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| H A D | AddressSanitizer.cpp | 652 Value *Addr, uint32_t TypeSize, bool IsWrite,
656 uint32_t TypeSize, bool IsWrite,
660 uint32_t TypeSize, bool IsWrite,
666 bool IsWrite, size_t AccessSizeIndex,
1455 bool IsWrite = F->getName().startswith("llvm.masked.store."); in getInterestingMemoryOperands() local
1457 unsigned OpOffset = IsWrite ? 1 : 0; in getInterestingMemoryOperands()
1458 if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads) in getInterestingMemoryOperands()
1470 Interesting.emplace_back(I, OpOffset, IsWrite, Ty, Alignment, Mask); in getInterestingMemoryOperands()
1540 uint32_t TypeSize, bool IsWrite, in doInstrumentAddress() argument
1548 return Pass->instrumentAddress(I, InsertBefore, Addr, TypeSize, IsWrite, in doInstrumentAddress()
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| H A D | HWAddressSanitizer.cpp | 219 void instrumentMemAccessInline(Value *Ptr, bool IsWrite,
733 void HWAddressSanitizer::instrumentMemAccessInline(Value *Ptr, bool IsWrite, in instrumentMemAccessInline() argument
742 (IsWrite << HWASanAccessInfo::IsWriteShift) + in instrumentMemAccessInline()
865 IRB.CreateCall(HwasanMemoryAccessCallback[O.IsWrite][AccessSizeIndex], in instrumentMemAccess()
868 instrumentMemAccessInline(Addr, O.IsWrite, AccessSizeIndex, O.getInsn()); in instrumentMemAccess()
871 IRB.CreateCall(HwasanMemoryAccessCallbackSized[O.IsWrite], in instrumentMemAccess()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Transforms/Instrumentation/ |
| H A D | AddressSanitizerCommon.h | 25 bool IsWrite; variable
32 InterestingMemoryOperand(Instruction *I, unsigned OperandNo, bool IsWrite,
35 : IsWrite(IsWrite), OpType(OpType), Alignment(Alignment), in IsWrite() argument
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| /netbsd-src/external/gpl3/gcc/dist/libsanitizer/tsan/ |
| H A D | tsan_shadow.h | 121 DCHECK_EQ(kAccessIsWrite, IsWrite()); in SetWrite()
167 bool ALWAYS_INLINE IsWrite() const { return !IsRead(); } in IsWrite() function
192 DCHECK_EQ(v, (!IsWrite() && !kIsWrite) || (IsAtomic() && kIsAtomic)); in IsBothReadsOrAtomic()
199 (IsAtomic() == kIsAtomic && !IsWrite() <= !kIsWrite)); in IsRWNotWeaker()
206 (IsAtomic() == kIsAtomic && !IsWrite() >= !kIsWrite)); in IsRWWeakerOrEqual()
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| H A D | tsan_rtl_report.cpp | 184 mop->write = s.IsWrite(); in AddMemoryAccess()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | LoopAccessAnalysis.cpp | 691 bool IsWrite = Access.getInt(); in createCheckForAccess() local
692 RtCheck.insert(TheLoop, Ptr, IsWrite, DepId, ASId, StridesMap, PSE); in createCheckForAccess()
732 bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); in canCheckPtrAtRT() local
734 if (IsWrite) in canCheckPtrAtRT()
738 AccessInfos.emplace_back(Ptr, IsWrite); in canCheckPtrAtRT()
893 bool IsWrite = AC.getInt(); in processMemAccesses() local
897 bool IsReadOnlyPtr = ReadOnlyPtr.count(Ptr) && !IsWrite; in processMemAccesses()
902 assert(((IsReadOnlyPtr && UseDeferred) || IsWrite || in processMemAccesses()
906 MemAccessInfo Access(Ptr, IsWrite); in processMemAccesses()
923 if ((IsWrite || IsReadOnlyPtr) && SetHasWrite) { in processMemAccesses()
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| /netbsd-src/external/gpl3/gcc.old/dist/libsanitizer/tsan/ |
| H A D | tsan_rtl.h | 211 DCHECK_EQ(kAccessIsWrite, IsWrite()); in SetWrite()
261 bool ALWAYS_INLINE IsWrite() const { return !IsRead(); } in IsWrite() function
290 DCHECK_EQ(v, (!IsWrite() && !kIsWrite) || (IsAtomic() && kIsAtomic)); in IsBothReadsOrAtomic()
298 (IsAtomic() == kIsAtomic && !IsWrite() <= !kIsWrite)); in IsRWNotWeaker()
306 (IsAtomic() == kIsAtomic && !IsWrite() >= !kIsWrite)); in IsRWWeakerOrEqual()
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| H A D | tsan_rtl_report.cc | 172 mop->write = s.IsWrite(); in AddMemoryAccess()
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| /netbsd-src/sys/external/bsd/compiler_rt/dist/lib/tsan/rtl/ |
| H A D | tsan_rtl.h | 215 DCHECK_EQ(kAccessIsWrite, IsWrite()); in SetWrite()
265 bool ALWAYS_INLINE IsWrite() const { return !IsRead(); } in IsWrite() function
294 DCHECK_EQ(v, (!IsWrite() && !kIsWrite) || (IsAtomic() && kIsAtomic)); in IsBothReadsOrAtomic()
302 (IsAtomic() == kIsAtomic && !IsWrite() <= !kIsWrite)); in IsRWNotWeaker()
310 (IsAtomic() == kIsAtomic && !IsWrite() >= !kIsWrite)); in IsRWWeakerOrEqual()
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| H A D | tsan_rtl_report.cc | 174 mop->write = s.IsWrite(); in AddMemoryAccess()
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| /netbsd-src/sys/external/bsd/compiler_rt/dist/lib/tsan/tests/unit/ |
| H A D | tsan_shadow_test.cc | 28 EXPECT_EQ(s.IsWrite(), true); in TEST()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 4139 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); in lowerPREFETCH() local
4140 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ; in lowerPREFETCH()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3183 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); in LowerPREFETCH() local
3199 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit in LowerPREFETCH()
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