| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 128 SDNode *Node, unsigned SEW, const SDLoc &DL, unsigned CurOp, bool IsMasked, in addVectorLoadStoreOperands() argument
143 if (IsMasked) { in addVectorLoadStoreOperands()
163 void RISCVDAGToDAGISel::selectVLSEG(SDNode *Node, bool IsMasked, in selectVLSEG() argument
173 if (IsMasked) { in selectVLSEG()
181 addVectorLoadStoreOperands(Node, ScalarSize, DL, CurOp, IsMasked, IsStrided, in selectVLSEG()
185 RISCV::getVLSEGPseudo(NF, IsMasked, IsStrided, /*FF*/ false, ScalarSize, in selectVLSEG()
204 void RISCVDAGToDAGISel::selectVLSEGFF(SDNode *Node, bool IsMasked) { in selectVLSEGFF() argument
214 if (IsMasked) { in selectVLSEGFF()
222 addVectorLoadStoreOperands(Node, ScalarSize, DL, CurOp, IsMasked, in selectVLSEGFF()
226 RISCV::getVLSEGPseudo(NF, IsMasked, /*Strided*/ false, /*FF*/ true, in selectVLSEGFF()
[all …]
|
| H A D | RISCVISelDAGToDAG.h | 77 bool IsMasked, bool IsStridedOrIndexed,
81 void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided);
82 void selectVLSEGFF(SDNode *Node, bool IsMasked);
83 void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
84 void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided);
85 void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
|
| H A D | RISCVExpandAtomicPseudoInsts.cpp | 52 bool IsMasked, int Width,
56 AtomicRMWInst::BinOp, bool IsMasked, int Width,
59 MachineBasicBlock::iterator MBBI, bool IsMasked,
343 AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width, in expandAtomicBinOp() argument
363 if (!IsMasked) in expandAtomicBinOp()
392 AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width, in expandAtomicMinMaxOp() argument
394 assert(IsMasked == true && in expandAtomicMinMaxOp()
512 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool IsMasked, in expandAtomicCmpXchg() argument
541 static_cast<AtomicOrdering>(MI.getOperand(IsMasked ? 6 : 5).getImm()); in expandAtomicCmpXchg()
543 if (!IsMasked) { in expandAtomicCmpXchg()
|
| H A D | RISCVISelLowering.cpp | 3412 bool IsMasked = NumOps == 6; in LowerINTRINSIC_WO_CHAIN() local
3413 unsigned OpOffset = IsMasked ? 1 : 0; in LowerINTRINSIC_WO_CHAIN()
3462 if (!IsMasked) in LowerINTRINSIC_WO_CHAIN()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | VFABIDemangling.cpp | 52 ParseRet tryParseMask(StringRef &MangledName, bool &IsMasked) { in tryParseMask() argument
54 IsMasked = true; in tryParseMask()
59 IsMasked = false; in tryParseMask()
338 bool IsMasked; in tryDemangleForVFABI() local
339 if (tryParseMask(MangledName, IsMasked) != ParseRet::OK) in tryDemangleForVFABI()
412 if (IsMasked) { in tryDemangleForVFABI()
|
| /netbsd-src/sys/external/bsd/acpica/dist/events/ |
| H A D | evgpe.c | 158 BOOLEAN IsMasked) in AcpiEvMaskGpe() argument
177 if (IsMasked) in AcpiEvMaskGpe()
|
| H A D | evxfgpe.c | 322 * IsMasked - Whether the GPE is masked or not in ACPI_EXPORT_SYMBOL()
335 BOOLEAN IsMasked) in ACPI_EXPORT_SYMBOL()
356 Status = AcpiEvMaskGpe (GpeEventInfo, IsMasked); in ACPI_EXPORT_SYMBOL()
|
| /netbsd-src/sys/external/bsd/acpica/dist/include/ |
| H A D | acevents.h | 136 BOOLEAN IsMasked);
|
| H A D | acpixf.h | 973 BOOLEAN IsMasked))
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/Disassembler/ |
| H A D | M68kDisassembler.cpp | 235 unsigned IsMasked = !(WordMask & Bit); in dump() local
241 char Ch = IsMasked ? '?' : (IsClear ? '0' : '1'); in dump()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4453 bool IsMasked = InMask.getNode() != nullptr; in tryVPTESTM() local
4473 if (IsMasked) { in tryVPTESTM()
4484 IsMasked); in tryVPTESTM()
4490 if (IsMasked) { in tryVPTESTM()
4505 if (IsMasked) in tryVPTESTM()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 15036 bool &IsLoad, bool &IsMasked, SDValue &Ptr, in getCombineLoadStoreParts() argument
15061 IsMasked = true; in getCombineLoadStoreParts()
15071 IsMasked = true; in getCombineLoadStoreParts()
15088 bool IsMasked = false; in CombineToPreIndexedLoadStore() local
15090 if (!getCombineLoadStoreParts(N, ISD::PRE_INC, ISD::PRE_DEC, IsLoad, IsMasked, in CombineToPreIndexedLoadStore()
15135 SDValue Val = IsMasked ? cast<MaskedStoreSDNode>(N)->getValue() in CombineToPreIndexedLoadStore()
15212 if (!IsMasked) { in CombineToPreIndexedLoadStore()
15326 bool IsMasked = false; in shouldCombineToPostInc() local
15329 IsMasked, OtherPtr, TLI)) { in shouldCombineToPostInc()
15349 bool &IsMasked, SDValue &Ptr, in getPostIndexedLoadStoreOp() argument
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 17878 bool isSEXTLoad, bool IsMasked, bool isLE, in getMVEIndexedAddressParts() argument
17889 bool CanChangeType = isLE && !IsMasked; in getMVEIndexedAddressParts()
17945 bool IsMasked = false; in getPreIndexedAddressParts() local
17960 IsMasked = true; in getPreIndexedAddressParts()
17965 IsMasked = true; in getPreIndexedAddressParts()
17974 Ptr.getNode(), VT, Alignment, isSEXTLoad, IsMasked, in getPreIndexedAddressParts()
18003 bool IsMasked = false; in getPostIndexedAddressParts() local
18021 IsMasked = true; in getPostIndexedAddressParts()
18027 IsMasked = true; in getPostIndexedAddressParts()
18051 getMVEIndexedAddressParts(Op, VT, Alignment, isSEXTLoad, IsMasked, in getPostIndexedAddressParts()
|