Searched refs:Interm (Results 1 – 1 of 1) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 6278 Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in splitScalarNotBinop() local
6280 MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), Interm) in splitScalarNotBinop()
6285 .addReg(Interm); in splitScalarNotBinop()
6307 Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in splitScalarBinOpN2() local
6309 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Interm) in splitScalarBinOpN2()
6314 .addReg(Interm); in splitScalarBinOpN2()
6531 Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); in splitScalar64BitXnor() local
6544 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B64), Interm) in splitScalar64BitXnor()
6550 .addReg(Interm) in splitScalar64BitXnor()
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