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Searched refs:IntVT (Results 1 – 21 of 21) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DValueTypes.h387 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local
388 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT()
389 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
H A DTargetLowering.h2070 virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, in shouldUseStrictFP_TO_INT() argument
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEISelLowering.cpp158 for (MVT IntVT : {MVT::i32, MVT::i64}) { in initSPUActions()
160 setOperationAction(ISD::UREM, IntVT, Expand); in initSPUActions()
161 setOperationAction(ISD::SREM, IntVT, Expand); in initSPUActions()
162 setOperationAction(ISD::SDIVREM, IntVT, Expand); in initSPUActions()
163 setOperationAction(ISD::UDIVREM, IntVT, Expand); in initSPUActions()
166 setOperationAction(ISD::SHL_PARTS, IntVT, Expand); in initSPUActions()
167 setOperationAction(ISD::SRA_PARTS, IntVT, Expand); in initSPUActions()
168 setOperationAction(ISD::SRL_PARTS, IntVT, Expand); in initSPUActions()
172 setOperationAction(ISD::MULHU, IntVT, Expand); in initSPUActions()
173 setOperationAction(ISD::MULHS, IntVT, Expand); in initSPUActions()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp444 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local
446 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo()
448 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
449 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
H A DFastISel.cpp304 EVT IntVT = TLI.getPointerTy(DL); in materializeConstant() local
305 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeConstant()
313 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant()
1617 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in selectFNeg() local
1618 if (!TLI.isTypeLegal(IntVT)) in selectFNeg()
1621 Register IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg()
1627 IntVT.getSimpleVT(), ISD::XOR, IntReg, in selectFNeg()
1628 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg()
1632 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
H A DLegalizeDAG.cpp1559 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFCOPYSIGN() local
1560 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFCOPYSIGN()
1561 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN()
1570 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1571 DAG.getConstant(0, DL, IntVT), ISD::SETNE); in ExpandFCOPYSIGN()
1585 EVT ShiftVT = IntVT; in ExpandFCOPYSIGN()
1613 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFNEG() local
1616 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFNEG()
1618 DAG.getNode(ISD::XOR, DL, IntVT, SignAsInt.IntValue, SignMask); in ExpandFNEG()
1638 EVT IntVT = ValueAsInt.IntValue.getValueType(); in ExpandFABS() local
[all …]
H A DTargetLowering.cpp6678 EVT IntVT = SrcVT.changeTypeToInteger(); in expandFP_TO_SINT() local
6679 EVT IntShVT = getShiftAmountTy(IntVT, DAG.getDataLayout()); in expandFP_TO_SINT()
6681 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); in expandFP_TO_SINT()
6682 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); in expandFP_TO_SINT()
6683 SDValue Bias = DAG.getConstant(127, dl, IntVT); in expandFP_TO_SINT()
6684 SDValue SignMask = DAG.getConstant(APInt::getSignMask(SrcEltBits), dl, IntVT); in expandFP_TO_SINT()
6685 SDValue SignLowBit = DAG.getConstant(SrcEltBits - 1, dl, IntVT); in expandFP_TO_SINT()
6686 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); in expandFP_TO_SINT()
6688 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Src); in expandFP_TO_SINT()
6691 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
[all …]
H A DLegalizeFloatTypes.cpp922 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in findFPToIntLibcall() local
923 IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; in findFPToIntLibcall()
924 ++IntVT) { in findFPToIntLibcall()
925 Promoted = (MVT::SimpleValueType)IntVT; in findFPToIntLibcall()
H A DSelectionDAG.cpp6182 EVT IntVT = VT.getScalarType(); in getMemsetValue() local
6183 if (!IntVT.isInteger()) in getMemsetValue()
6184 IntVT = EVT::getIntegerVT(*DAG.getContext(), IntVT.getSizeInBits()); in getMemsetValue()
6186 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value); in getMemsetValue()
6191 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value, in getMemsetValue()
6192 DAG.getConstant(Magic, dl, IntVT)); in getMemsetValue()
H A DDAGCombiner.cpp12732 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); in ConstantFoldBITCASTofBUILD_VECTOR() local
12733 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); in ConstantFoldBITCASTofBUILD_VECTOR()
12734 SrcEltVT = IntVT; in ConstantFoldBITCASTofBUILD_VECTOR()
16595 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VTSize.getFixedSize()); in TransformFPLoadStorePair() local
16596 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || in TransformFPLoadStorePair()
16597 !TLI.isOperationLegal(ISD::STORE, IntVT) || in TransformFPLoadStorePair()
16604 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); in TransformFPLoadStorePair()
16610 DAG.getLoad(IntVT, SDLoc(Value), LD->getChain(), LD->getBasePtr(), in TransformFPLoadStorePair()
22201 EVT IntVT = Int.getValueType(); in foldSignChangeInBitcast() local
22204 if (!IntVT.isInteger() || IntVT.isVector()) in foldSignChangeInBitcast()
[all …]
H A DSelectionDAGBuilder.cpp247 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); in getCopyFromParts() local
248 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC); in getCopyFromParts()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp1684 EVT IntVT = MemVT.changeTypeToInteger(); in lowerKernargMemParameter() local
1696 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract); in lowerKernargMemParameter()
4647 EVT IntVT = LoadVT.changeTypeToInteger(); in lowerIntrinsicLoad() local
4663 return getMemIntrinsicNode(Opc, DL, M->getVTList(), Ops, IntVT, in lowerIntrinsicLoad()
5439 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerINSERT_VECTOR_ELT() local
5446 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT, in lowerINSERT_VECTOR_ELT()
5455 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec); in lowerINSERT_VECTOR_ELT()
5456 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT, in lowerINSERT_VECTOR_ELT()
5457 DAG.getConstant(0xffff, SL, IntVT), in lowerINSERT_VECTOR_ELT()
5460 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT()
[all …]
H A DAMDGPUISelLowering.cpp1662 MVT IntVT = MVT::i32; in LowerDIVREM24() local
1682 SDValue jq = DAG.getConstant(1, DL, IntVT); in LowerDIVREM24()
1729 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq); in LowerDIVREM24()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp718 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); in initActions() local
719 if (IntVT.isValid()) { in initActions()
721 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); in initActions()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp3570 MVT IntVT = is64Bit() ? MVT::i64 : MVT::i32; in forwardMustTailParameters() local
3571 RegParmTypes.push_back(IntVT); in forwardMustTailParameters()
19830 MVT IntVT = CastToInt.getSimpleValueType(); in lowerFPToIntToFP() local
19839 IntVT != MVT::i32) in lowerFPToIntToFP()
19843 unsigned IntSize = IntVT.getSizeInBits(); in lowerFPToIntToFP()
19846 MVT VecIntVT = MVT::getVectorVT(IntVT, 128 / IntSize); in lowerFPToIntToFP()
22125 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); in LowerVectorAllZero() local
22126 if (!DAG.getTargetLoweringInfo().isTypeLegal(IntVT)) in LowerVectorAllZero()
22129 DAG.getBitcast(IntVT, MaskBits(V)), in LowerVectorAllZero()
22130 DAG.getConstant(0, DL, IntVT)); in LowerVectorAllZero()
[all …]
H A DX86ISelDAGToDAG.cpp1133 EVT IntVT = EVT(VecVT).changeVectorElementTypeToInteger(); in PreprocessISelDAG() local
1134 Op0 = CurDAG->getNode(ISD::BITCAST, dl, IntVT, Op0); in PreprocessISelDAG()
1135 Op1 = CurDAG->getNode(ISD::BITCAST, dl, IntVT, Op1); in PreprocessISelDAG()
1144 Res = CurDAG->getNode(Opc, dl, IntVT, Op0, Op1); in PreprocessISelDAG()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3985 MVT IntVT = VecVT.changeVectorElementTypeToInteger(); in lowerVECTOR_REVERSE() local
4014 IntVT = MVT::getVectorVT(MVT::i16, VecVT.getVectorElementCount()); in lowerVECTOR_REVERSE()
4031 !Subtarget.is64Bit() && IntVT.getVectorElementType() == MVT::i64; in lowerVECTOR_REVERSE()
4034 SplatVL = DAG.getSplatVector(IntVT, DL, VLMinus1); in lowerVECTOR_REVERSE()
4036 SplatVL = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, IntVT, VLMinus1); in lowerVECTOR_REVERSE()
4038 SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, IntVT, Mask, VL); in lowerVECTOR_REVERSE()
4040 DAG.getNode(RISCVISD::SUB_VL, DL, IntVT, SplatVL, VID, Mask, VL); in lowerVECTOR_REVERSE()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5233 MVT IntVT = MVT::getIntegerVT(VT.getScalarSizeInBits()); in lowerINSERT_VECTOR_ELT() local
5234 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements()); in lowerINSERT_VECTOR_ELT()
5237 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2); in lowerINSERT_VECTOR_ELT()
5260 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits()); in lowerEXTRACT_VECTOR_ELT() local
5261 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements()); in lowerEXTRACT_VECTOR_ELT()
5262 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, in lowerEXTRACT_VECTOR_ELT()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp970 MVT IntVT = MVT::i32; in LowerFormalArguments() local
971 RegParmTypes.push_back(IntVT); in LowerFormalArguments()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12339 EVT IntVT = BV->getValueType(0); in performVectorCompareAndMaskUnaryOpCombine() local
12344 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst); in performVectorCompareAndMaskUnaryOpCombine()
12345 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT, in performVectorCompareAndMaskUnaryOpCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp7517 EVT IntVT = Op.getValueType(); in LowerGET_DYNAMIC_AREA_OFFSET() local
7524 SDVTList VTs = DAG.getVTList(IntVT); in LowerGET_DYNAMIC_AREA_OFFSET()