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Searched refs:Instr (Results 1 – 25 of 130) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-cfi-verify/lib/
H A DFileAnalysis.h78 struct Instr { struct
98 const Instr *getInstruction(uint64_t Address) const;
102 const Instr &getInstructionOrDie(uint64_t Address) const;
107 const Instr *getPrevInstructionSequential(const Instr &InstrMeta) const;
108 const Instr *getNextInstructionSequential(const Instr &InstrMeta) const;
111 bool isCFITrap(const Instr &InstrMeta) const;
115 bool willTrapOnCFIViolation(const Instr &InstrMeta) const;
121 bool canFallThrough(const Instr &InstrMeta) const;
130 const Instr *getDefiniteNextInstruction(const Instr &InstrMeta) const;
135 std::set<const Instr *>
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H A DFileAnalysis.cpp39 using Instr = llvm::cfi_verify::FileAnalysis::Instr; typedef
121 const Instr *
122 FileAnalysis::getPrevInstructionSequential(const Instr &InstrMeta) const { in getPrevInstructionSequential()
123 std::map<uint64_t, Instr>::const_iterator KV = in getPrevInstructionSequential()
134 const Instr *
135 FileAnalysis::getNextInstructionSequential(const Instr &InstrMeta) const { in getNextInstructionSequential()
136 std::map<uint64_t, Instr>::const_iterator KV = in getNextInstructionSequential()
147 bool FileAnalysis::usesRegisterOperand(const Instr &InstrMeta) const { in usesRegisterOperand()
155 const Instr *FileAnalysis::getInstruction(uint64_t Address) const { in getInstruction()
163 const Instr &FileAnalysis::getInstructionOrDie(uint64_t Address) const { in getInstructionOrDie()
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H A DGraphBuilder.cpp36 using Instr = llvm::cfi_verify::FileAnalysis::Instr; typedef
115 const Instr &BranchInstrMeta) { in buildFlowsToUndefined()
121 const Instr *NextMetaPtr; in buildFlowsToUndefined()
166 const Instr *CurrentMetaPtr = NextMetaPtr; in buildFlowsToUndefined()
226 std::set<const Instr *> CFCrossRefs = in buildFlowGraphImpl()
326 const Instr *PrevInstr = Analysis.getPrevInstructionSequential(ChildMeta); in buildFlowGraphImpl()
H A DGraphBuilder.h44 using Instr = llvm::cfi_verify::FileAnalysis::Instr; variable
130 const Instr &BranchInstrMeta);
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp58 static const char *isInvalidMemoryInstr(const Instruction &Instr) { in isInvalidMemoryInstr() argument
59 switch (Instr.Description.TSFlags & X86II::FormMask) { in isInvalidMemoryInstr()
158 return (Instr.Description.Opcode == X86::POP16r || in isInvalidMemoryInstr()
159 Instr.Description.Opcode == X86::POP32r || in isInvalidMemoryInstr()
160 Instr.Description.Opcode == X86::PUSH16r || in isInvalidMemoryInstr()
161 Instr.Description.Opcode == X86::PUSH32r) in isInvalidMemoryInstr()
193 static const char *isInvalidOpcode(const Instruction &Instr) { in isInvalidOpcode() argument
194 const auto OpcodeName = Instr.Name; in isInvalidOpcode()
195 if ((Instr.Description.TSFlags & X86II::FormMask) == X86II::Pseudo) in isInvalidOpcode()
201 switch (Instr.Description.Opcode) { in isInvalidOpcode()
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/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
H A DCodeTemplate.cpp18 InstructionTemplate::InstructionTemplate(const Instruction *Instr) in InstructionTemplate() argument
19 : Instr(Instr), VariableValues(Instr->Variables.size()) {} in InstructionTemplate()
32 return Instr->Description.getOpcode(); in getOpcode()
44 return getValueFor(Instr->Variables[Op.getVariableIndex()]); in getValueFor()
48 return getValueFor(Instr->Variables[Op.getVariableIndex()]); in getValueFor()
52 return any_of(Instr->Variables, [this](const Variable &Var) { in hasImmediateVariables()
53 return Instr->getPrimaryOperand(Var).isImmediate(); in hasImmediateVariables()
59 Result.setOpcode(Instr->Description.Opcode); in build()
60 for (const auto &Op : Instr->Operands) in build()
H A DSerialSnippetGenerator.cpp38 computeAliasingInstructions(const LLVMState &State, const Instruction *Instr, in computeAliasingInstructions() argument
49 if (OtherOpcode == Instr->Description.getOpcode()) in computeAliasingInstructions()
63 if (Instr->hasAliasingRegistersThrough(OtherInstr, ForbiddenRegisters)) in computeAliasingInstructions()
71 static ExecutionMode getExecutionModes(const Instruction &Instr, in getExecutionModes() argument
74 if (Instr.hasAliasingImplicitRegisters()) in getExecutionModes()
76 if (Instr.hasTiedRegisters()) in getExecutionModes()
78 if (Instr.hasMemoryOperands()) in getExecutionModes()
81 if (Instr.hasAliasingRegisters(ForbiddenRegisters)) in getExecutionModes()
83 if (Instr.hasOneUseOrOneDef()) in getExecutionModes()
133 const Instruction &Instr = Variant.getInstr(); in appendCodeTemplates() local
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H A DParallelSnippetGenerator.cpp83 getVariablesWithTiedOperands(const Instruction &Instr) { in getVariablesWithTiedOperands() argument
85 for (const auto &Var : Instr.Variables) in getVariablesWithTiedOperands()
160 const Instruction &Instr = Variant.getInstr(); in generateCodeTemplates() local
163 Instr.hasMemoryOperands() in generateCodeTemplates()
167 const AliasingConfigurations SelfAliasing(Instr, Instr); in generateCodeTemplates()
180 const auto TiedVariables = getVariablesWithTiedOperands(Instr); in generateCodeTemplates()
190 for (const auto &Op : Instr.Operands) { in generateCodeTemplates()
203 for (const auto &Op : Instr.Operands) { in generateCodeTemplates()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMFeatures.h21 bool IsCPSRDead(const InstrType *Instr);
24 inline bool isV8EligibleForIT(const InstrType *Instr) { in isV8EligibleForIT() argument
25 switch (Instr->getOpcode()) { in isV8EligibleForIT()
52 return IsCPSRDead(Instr); in isV8EligibleForIT()
79 return Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
84 return Instr->getOperand(0).getReg() != ARM::PC; in isV8EligibleForIT()
86 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
87 Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
90 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
91 Instr->getOperand(1).getReg() != ARM::PC; in isV8EligibleForIT()
H A DMVETPAndVPTOptimisationsPass.cpp71 MachineInstr &Instr,
536 static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) { in GetCondCode() argument
537 assert(IsVCMP(Instr.getOpcode()) && "Inst must be a VCMP"); in GetCondCode()
538 return ARMCC::CondCodes(Instr.getOperand(3).getImm()); in GetCondCode()
569 static bool IsWritingToVCCR(MachineInstr &Instr) { in IsWritingToVCCR() argument
570 if (Instr.getNumOperands() == 0) in IsWritingToVCCR()
572 MachineOperand &Dst = Instr.getOperand(0); in IsWritingToVCCR()
578 MachineRegisterInfo &RegInfo = Instr.getMF()->getRegInfo(); in IsWritingToVCCR()
592 MachineBasicBlock &MBB, MachineInstr &Instr, MachineOperand &User, in ReplaceRegisterUseWithVPNOT() argument
597 BuildMI(MBB, &Instr, Instr.getDebugLoc(), TII->get(ARM::MVE_VPNOT)) in ReplaceRegisterUseWithVPNOT()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/Disassembler/
H A DM68kDisassembler.cpp126 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
129 void decodeReg(MCInst &Instr, unsigned int Bead,
131 void decodeImm(MCInst &Instr, unsigned int Bead,
133 unsigned int getRegOperandIndex(MCInst &Instr, unsigned int Bead) const;
134 unsigned int getImmOperandIndex(MCInst &Instr, unsigned int Bead) const;
371 unsigned M68kDisassembler::getRegOperandIndex(MCInst &Instr, in getRegOperandIndex() argument
375 const MCInstrDesc &Desc = MCII->get(Instr.getOpcode()); in getRegOperandIndex()
376 auto MIOpIdx = M68k::getLogicalOperandIdx(Instr.getOpcode(), Ext & 7); in getRegOperandIndex()
378 if (M68kII::hasMultiMIOperands(Instr.getOpcode(), Ext & 7)) { in getRegOperandIndex()
391 unsigned M68kDisassembler::getImmOperandIndex(MCInst &Instr, in getImmOperandIndex() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
H A DCorrelatedValuePropagation.cpp672 static bool narrowSDivOrSRem(BinaryOperator *Instr, LazyValueInfo *LVI) { in narrowSDivOrSRem() argument
673 assert(Instr->getOpcode() == Instruction::SDiv || in narrowSDivOrSRem()
674 Instr->getOpcode() == Instruction::SRem); in narrowSDivOrSRem()
675 if (Instr->getType()->isVectorTy()) in narrowSDivOrSRem()
680 unsigned OrigWidth = Instr->getType()->getIntegerBitWidth(); in narrowSDivOrSRem()
686 for (auto I : zip(Instr->operands(), CRs)) { in narrowSDivOrSRem()
687 std::get<1>(I) = LVI->getConstantRange(std::get<0>(I), Instr); in narrowSDivOrSRem()
707 IRBuilder<> B{Instr}; in narrowSDivOrSRem()
708 auto *TruncTy = Type::getIntNTy(Instr->getContext(), NewWidth); in narrowSDivOrSRem()
709 auto *LHS = B.CreateTruncOrBitCast(Instr->getOperand(0), TruncTy, in narrowSDivOrSRem()
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H A DGuardWidening.cpp136 Instruction *Instr, const df_iterator<DomTreeNode *> &DFSI,
328 Instruction *Instr, const df_iterator<DomTreeNode *> &DFSI, in eliminateInstrViaWidening() argument
334 if (isa<ConstantInt>(getCondition(Instr))) in eliminateInstrViaWidening()
350 auto E = Instr->getParent() == CurBB ? find(GuardsInCurBB, Instr) in eliminateInstrViaWidening()
367 assert((i == (e - 1)) == (Instr->getParent() == CurBB) && "Bad DFS?"); in eliminateInstrViaWidening()
370 auto Score = computeWideningScore(Instr, Candidate, InvertCondition); in eliminateInstrViaWidening()
371 LLVM_DEBUG(dbgs() << "Score between " << *getCondition(Instr) in eliminateInstrViaWidening()
382 LLVM_DEBUG(dbgs() << "Did not eliminate guard " << *Instr << "\n"); in eliminateInstrViaWidening()
386 assert(BestSoFar != Instr && "Should have never visited same guard!"); in eliminateInstrViaWidening()
387 assert(DT.dominates(BestSoFar, Instr) && "Should be!"); in eliminateInstrViaWidening()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp51 MachineInstr *Instr; member in __anon11f0a5620111::RegSeqInfo
55 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { in RegSeqInfo()
57 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) { in RegSeqInfo()
58 MachineOperand &MO = Instr->getOperand(i); in RegSeqInfo()
59 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo()
70 return RSI.Instr == Instr; in operator ==()
185 Register Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
186 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
190 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector()
226 RSI->Instr->eraseFromParent(); in RebuildVector()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
94 if (isRMOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
96 else if (isSPLSOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
98 else if (isRRMOpcode(Instr.getOpcode())) { in PostOperandDecodeAdjust()
112 if (Instr.getOperand(2).isReg()) { in PostOperandDecodeAdjust()
113 Instr.getOperand(2).setReg(Lanai::R0); in PostOperandDecodeAdjust()
115 if (Instr.getOperand(2).isImm()) in PostOperandDecodeAdjust()
116 Instr.getOperand(2).setImm(0); in PostOperandDecodeAdjust()
127 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
132 LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyDebugValueManager.cpp22 MachineInstr *Instr) { in WebAssemblyDebugValueManager() argument
23 const auto *MF = Instr->getParent()->getParent(); in WebAssemblyDebugValueManager()
28 if (!Instr->getOperand(0).isReg()) in WebAssemblyDebugValueManager()
30 CurrentReg = Instr->getOperand(0).getReg(); in WebAssemblyDebugValueManager()
33 MachineBasicBlock::iterator DI = *Instr; in WebAssemblyDebugValueManager()
35 for (MachineBasicBlock::iterator DE = Instr->getParent()->end(); DI != DE; in WebAssemblyDebugValueManager()
38 DI->hasDebugOperandForReg(Instr->getOperand(0).getReg())) in WebAssemblyDebugValueManager()
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/GlobalISel/
H A DGIMatchDagPredicate.cpp27 GIMatchDagContext &Ctx, StringRef Name, const CodeGenInstruction &Instr) in GIMatchDagOpcodePredicate() argument
30 Instr(Instr) {} in GIMatchDagOpcodePredicate()
33 OS << "$mi.getOpcode() == " << Instr.TheDef->getName(); in printDescription()
44 for (const CodeGenInstruction *Instr : Instrs) { in printDescription() local
45 OS << Separator << Instr->TheDef->getName(); in printDescription()
H A DGIMatchDagPredicate.h80 const CodeGenInstruction &Instr; variable
84 const CodeGenInstruction &Instr);
90 const CodeGenInstruction *getInstr() const { return &Instr; } in getInstr()
105 void addOpcode(const CodeGenInstruction *Instr) { Instrs.push_back(Instr); } in addOpcode() argument
H A DGIMatchTree.cpp109 void GIMatchTreeBuilderLeafInfo::declareInstr(const GIMatchDagInstr *Instr, unsigned ID) { in declareInstr() argument
112 Instr, GIMatchTreeInstrInfo(ID, Instr))); in declareInstr()
115 if (Instr == nullptr) in declareInstr()
118 if (!Instr->getUserAssignedName().empty()) in declareInstr()
119 Info.bindInstrVariable(Instr->getUserAssignedName(), ID); in declareInstr()
120 for (const auto &VarBinding : Instr->user_assigned_operand_names()) in declareInstr()
124 const auto &NodeI = find(MatchDag.instr_nodes(), Instr); in declareInstr()
138 if (Dep.value()->getRequiredMI() == Instr && in declareInstr()
151 const GIMatchDagInstr *Instr = InstrIDToInfo.lookup(InstrID)->getInstrNode(); in declareOperand() local
155 GIMatchTreeOperandInfo(Instr, OpIdx))); in declareOperand()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp68 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
164 DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
181 Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address, in getInstruction()
184 Result = decodeInstruction(DecoderTableBPF64, Instr, Insn, Address, this, in getInstruction()
189 switch (Instr.getOpcode()) { in getInstruction()
201 auto& Op = Instr.getOperand(1); in getInstruction()
211 auto Op = Instr.getOperand(0); in getInstruction()
212 Instr.clear(); in getInstruction()
213 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
214 Instr.addOperand(Op); in getInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
H A DVectorUtils.h588 InterleaveGroup(InstTy *Instr, int32_t Stride, Align Alignment) in InterleaveGroup() argument
589 : Alignment(Alignment), InsertPos(Instr) { in InterleaveGroup()
594 Members[0] = Instr; in InterleaveGroup()
607 bool insertMember(InstTy *Instr, int32_t Index, Align NewAlign) { in insertMember() argument
645 Members[Key] = Instr; in insertMember()
659 uint32_t getIndex(const InstTy *Instr) const { in getIndex() argument
661 if (I.second == Instr) in getIndex()
763 bool isInterleaved(Instruction *Instr) const { in isInterleaved() argument
764 return InterleaveGroupMap.find(Instr) != InterleaveGroupMap.end(); in isInterleaved()
771 getInterleaveGroup(const Instruction *Instr) const { in getInterleaveGroup() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64PromoteConstant.cpp272 static bool shouldConvertUse(const Constant *Cst, const Instruction *Instr, in shouldConvertUse() argument
276 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2) in shouldConvertUse()
280 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) in shouldConvertUse()
284 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) in shouldConvertUse()
287 if (isa<const AllocaInst>(Instr) && OpIdx > 0) in shouldConvertUse()
291 if (isa<const LoadInst>(Instr) && OpIdx > 0) in shouldConvertUse()
295 if (isa<const StoreInst>(Instr) && OpIdx > 1) in shouldConvertUse()
299 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) in shouldConvertUse()
304 if (isa<const LandingPadInst>(Instr)) in shouldConvertUse()
308 if (isa<const SwitchInst>(Instr)) in shouldConvertUse()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DDbgEntityHistoryCalculator.h79 Entry(const MachineInstr *Instr, EntryKind Kind) in Entry() argument
80 : Instr(Instr, Kind), EndIndex(NoEntry) {} in Entry()
82 const MachineInstr *getInstr() const { return Instr.getPointer(); } in getInstr()
84 EntryKind getEntryKind() const { return Instr.getInt(); } in getEntryKind()
93 PointerIntPair<const MachineInstr *, 1, EntryKind> Instr;
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DRegBankSelect.h207 MachineInstr &Instr;
216 return Instr; in getPointImpl()
217 return Instr.getNextNode() ? *Instr.getNextNode() in getPointImpl()
218 : Instr.getParent()->end(); in getPointImpl()
222 return *Instr.getParent(); in getInsertMBBImpl()
227 InstrInsertPoint(MachineInstr &Instr, bool Before = true);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/ExecutionEngine/JITLink/
H A DMachO_arm64.cpp297 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local
298 if ((Instr & 0x7fffffff) != 0x14000000) in addRelocations()
332 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local
333 if ((Instr & 0xffffffe0) != 0x90000000) in addRelocations()
344 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local
345 uint32_t EncodedAddend = (Instr & 0x003FFC00) >> 10; in addRelocations()
356 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local
357 if ((Instr & 0xfffffc00) != 0xf9400000) in addRelocations()
513 static unsigned getPageOffset12Shift(uint32_t Instr) { in getPageOffset12Shift() argument
517 if ((Instr & LoadStoreImm12Mask) == 0x39000000) { in getPageOffset12Shift()
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