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Searched refs:InputArg (Results 1 – 25 of 59) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/clang/lib/Driver/
H A DInputInfo.h32 InputArg, enumerator
38 const llvm::opt::Arg *InputArg; member
65 : Kind(InputArg), Act(nullptr), Type(_Type), BaseInput(_BaseInput) { in InputInfo()
66 Data.InputArg = _InputArg; in InputInfo()
70 : Kind(InputArg), Act(A), Type(GetActionType(A)), BaseInput(_BaseInput) { in InputInfo()
71 Data.InputArg = _InputArg; in InputInfo()
76 bool isInputArg() const { return Kind == InputArg; } in isInputArg()
89 return *Data.InputArg; in getInputArg()
H A DDriver.cpp2327 Arg *InputArg = MakeInputArg(Args, Opts, A->getValue()); in BuildInputs() local
2328 Inputs.push_back(std::make_pair(types::TY_C, InputArg)); in BuildInputs()
2335 Arg *InputArg = MakeInputArg(Args, Opts, A->getValue()); in BuildInputs() local
2336 Inputs.push_back(std::make_pair(types::TY_CXX, InputArg)); in BuildInputs()
3318 addDeviceDependencesToHostAction(Action *HostAction, const Arg *InputArg, in addDeviceDependencesToHostAction() argument
3332 auto &OffloadKind = InputArgToOffloadKindMap[InputArg]; in addDeviceDependencesToHostAction()
3377 const Arg *InputArg) { in addHostDependenceToDeviceActions() argument
3388 InputArg->getOption().getKind() == llvm::opt::Option::InputClass && in addHostDependenceToDeviceActions()
3402 auto &OffloadKind = InputArgToOffloadKindMap[InputArg]; in addHostDependenceToDeviceActions()
3432 const Arg *InputArg) { in appendTopLevelActions() argument
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsCCState.h32 void PreAnalyzeCallResultForF128(const SmallVectorImpl<ISD::InputArg> &Ins,
49 PreAnalyzeFormalArgumentsForF128(const SmallVectorImpl<ISD::InputArg> &Ins);
52 PreAnalyzeCallResultForVectorFloat(const SmallVectorImpl<ISD::InputArg> &Ins,
56 const SmallVectorImpl<ISD::InputArg> &Ins);
110 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeFormalArguments()
119 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeCallResult()
H A DMipsCCState.cpp87 const SmallVectorImpl<ISD::InputArg> &Ins, in PreAnalyzeCallResultForF128()
112 const SmallVectorImpl<ISD::InputArg> &Ins, const Type *RetTy) { in PreAnalyzeCallResultForVectorFloat()
148 const SmallVectorImpl<ISD::InputArg> &Ins) { in PreAnalyzeFormalArgumentsForF128()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h118 const SmallVectorImpl<ISD::InputArg> &Ins,
124 const SmallVectorImpl<ISD::InputArg> &Ins,
130 const SmallVectorImpl<ISD::InputArg> &Ins,
139 const SmallVectorImpl<ISD::InputArg> &Ins,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h146 const SmallVectorImpl<ISD::InputArg> &Ins,
152 const SmallVectorImpl<ISD::InputArg> &Ins,
158 const SmallVectorImpl<ISD::InputArg> &Ins,
164 const SmallVectorImpl<ISD::InputArg> &Ins,
H A DMSP430ISelLowering.cpp446 const SmallVectorImpl<ISD::InputArg> &Ins) { in AnalyzeVarArgs()
550 const SmallVectorImpl<ISD::InputArg> &Ins) { in AnalyzeRetResult()
568 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerFormalArguments()
591 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall()
619 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCCCArguments()
807 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCCCCallTo()
935 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCallResult()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kISelLowering.h194 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
223 const SmallVectorImpl<ISD::InputArg> &Ins,
231 const SmallVectorImpl<ISD::InputArg> &Ins,
270 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h1173 const SmallVectorImpl<ISD::InputArg> &Ins,
1179 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
1238 const SmallVectorImpl<ISD::InputArg> &Ins,
1246 const SmallVectorImpl<ISD::InputArg> &Ins,
1252 const SmallVectorImpl<ISD::InputArg> &Ins,
1275 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1279 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1283 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1294 const SmallVectorImpl<ISD::InputArg> &Ins,
1301 const SmallVectorImpl<ISD::InputArg> &Ins,
[all …]
H A DPPCCCState.h25 PreAnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins);
50 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeFormalArguments()
H A DPPCCCState.cpp27 const SmallVectorImpl<ISD::InputArg> &Ins) { in PreAnalyzeFormalArguments()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetCallingConv.h195 struct InputArg { struct
211 InputArg() = default; argument
212 InputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool used, in InputArg() function
H A DCallingConvLower.h283 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
287 void AnalyzeArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeArguments()
322 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
525 const SmallVectorImpl<ISD::InputArg> &Ins,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h121 const SmallVectorImpl<ISD::InputArg> &Ins,
126 const SmallVectorImpl<ISD::InputArg> &Ins,
131 const SmallVectorImpl<ISD::InputArg> &Ins,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h148 const SmallVectorImpl<ISD::InputArg> &Ins,
156 const SmallVectorImpl<ISD::InputArg> &Ins,
212 const SmallVectorImpl<ISD::InputArg> &Ins,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCISelLowering.h83 const SmallVectorImpl<ISD::InputArg> &Ins,
97 const SmallVectorImpl<ISD::InputArg> &Ins,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h54 const ISD::InputArg *Arg = nullptr) const;
58 const ISD::InputArg &Arg) const;
131 bool Signed, const ISD::InputArg *Arg = nullptr) const;
322 const SmallVectorImpl<ISD::InputArg> &Ins,
346 const SmallVectorImpl<ISD::InputArg> &Ins,
357 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
H A DR600ISelLowering.h43 const SmallVectorImpl<ISD::InputArg> &Ins,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFISelLowering.h82 const SmallVectorImpl<ISD::InputArg> &Ins,
96 const SmallVectorImpl<ISD::InputArg> &Ins,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DCallingConvLower.cpp90 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeFormalArguments()
167 void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeCallResult()
269 const SmallVectorImpl<ISD::InputArg> &Ins, in resultsCompatible()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.h174 const SmallVectorImpl<ISD::InputArg> &Ins,
181 const SmallVectorImpl<ISD::InputArg> &Ins,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h126 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
193 const SmallVectorImpl<ISD::InputArg> &Ins,
214 const SmallVectorImpl<ISD::InputArg> &Ins,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.h1457 const SmallVectorImpl<ISD::InputArg> &Ins,
1462 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
1483 const SmallVectorImpl<ISD::InputArg> &Ins,
1551 const SmallVectorImpl<ISD::InputArg> &Ins,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h415 const SmallVectorImpl<ISD::InputArg> &Ins,
485 const SmallVectorImpl<ISD::InputArg> &Ins,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.h51 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeFormalArguments()

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