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Searched refs:InOrderIssueStage (Results 1 – 7 of 7) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/
H A DInOrderIssueStage.h31 class InOrderIssueStage final : public Stage {
61 InOrderIssueStage(const InOrderIssueStage &Other) = delete;
62 InOrderIssueStage &operator=(const InOrderIssueStage &Other) = delete;
82 InOrderIssueStage(RegisterFile &PRF, const MCSchedModel &SM, in InOrderIssueStage() function
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
H A DInOrderIssueStage.cpp31 bool InOrderIssueStage::hasWorkToComplete() const { in hasWorkToComplete()
35 bool InOrderIssueStage::isAvailable(const InstRef &IR) const { in isAvailable()
144 bool InOrderIssueStage::canExecute(const InstRef &IR, in canExecute()
211 llvm::Error InOrderIssueStage::execute(InstRef &IR) { in execute()
222 llvm::Error InOrderIssueStage::tryIssue(InstRef &IR, unsigned *StallCycles) { in tryIssue()
274 void InOrderIssueStage::updateIssuedInst() { in updateIssuedInst()
306 void InOrderIssueStage::updateCarriedOver() { in updateCarriedOver()
332 void InOrderIssueStage::retireInstruction(InstRef &IR) { in retireInstruction()
344 llvm::Error InOrderIssueStage::cycleStart() { in cycleStart()
377 llvm::Error InOrderIssueStage::cycleEnd() { in cycleEnd()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/
H A DCMakeLists.txt17 Stages/InOrderIssueStage.cpp
H A DContext.cpp77 auto InOrderIssue = std::make_unique<InOrderIssueStage>(*PRF, SM, STI); in createInOrderPipeline()
/netbsd-src/external/apache2/llvm/dist/llvm/utils/gn/secondary/llvm/lib/MCA/
H A DBUILD.gn25 "Stages/InOrderIssueStage.cpp",
/netbsd-src/external/apache2/llvm/lib/libLLVMMCA/
H A DMakefile12 InOrderIssueStage.cpp \
/netbsd-src/external/apache2/llvm/dist/llvm/docs/CommandGuide/
H A Dllvm-mca.rst971 In-order processors are modelled as a single ``InOrderIssueStage`` stage. It