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Searched refs:ImplicitUses (Results 1 – 11 of 11) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCInstrDesc.h204 const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr variable
559 const MCPhysReg *getImplicitUses() const { return ImplicitUses; } in getImplicitUses()
563 if (!ImplicitUses) in getNumImplicitUses()
566 for (; ImplicitUses[i]; ++i) /*empty*/ in getNumImplicitUses()
596 if (const MCPhysReg *ImpUses = ImplicitUses) in hasImplicitUseOfPhysReg()
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DInstrDocsEmitter.cpp198 if (!II->ImplicitUses.empty()) { in EmitInstrDocs()
201 for (Record *Use : II->ImplicitUses) in EmitInstrDocs()
H A DCodeGenInstruction.h233 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
H A DCodeGenInstruction.cpp420 ImplicitUses = R->getValueAsListOfDefs("Uses"); in CodeGenInstruction()
H A DGlobalISelEmitter.cpp3097 if (!I->ImplicitDefs.empty() || !I->ImplicitUses.empty()) { in emitActionOpcodes()
3107 for (auto Use : I->ImplicitUses) { in emitActionOpcodes()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp166 if (const MCPhysReg *R = D.ImplicitUses) in getDefsUses()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineInstr.cpp109 if (MCID->ImplicitUses) in addImplicitDefUseOperands()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp1207 if (MCID.ImplicitUses) in verifyImplicitOperands()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2714 if (NewDesc.ImplicitUses) in optimizeCompareInstr()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3136 unsigned Reg = Desc.ImplicitUses[i]; in findImplicitSGPRReadInVOP()
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DCodeGenerator.rst1326 ``TargetInstrInfo::get(opcode)::ImplicitUses``. Pre-colored registers impose