| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 205 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr variable
581 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } in getImplicitDefs()
585 if (!ImplicitDefs) in getNumImplicitDefs()
588 for (; ImplicitDefs[i]; ++i) /*empty*/ in getNumImplicitDefs()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineCSE.cpp | 516 SmallVector<unsigned, 2> ImplicitDefs; in ProcessBlockCSE() local
627 ImplicitDefs.push_back(OldReg); in ProcessBlockCSE()
692 for (auto ImplicitDef : ImplicitDefs) in ProcessBlockCSE()
699 for (auto ImplicitDef : ImplicitDefs) in ProcessBlockCSE()
727 ImplicitDefs.clear(); in ProcessBlockCSE()
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| H A D | MachineInstr.cpp | 105 if (MCID->ImplicitDefs) in addImplicitDefUseOperands()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | InstrDocsEmitter.cpp | 189 if (!II->ImplicitDefs.empty()) { in EmitInstrDocs()
192 for (Record *Def : II->ImplicitDefs) in EmitInstrDocs()
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| H A D | CodeGenInstruction.cpp | 419 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
454 if (ImplicitDefs.empty()) return MVT::Other; in HasOneImplicitDefWithKnownVT()
457 Record *FirstImplicitDef = ImplicitDefs[0]; in HasOneImplicitDefWithKnownVT()
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| H A D | CodeGenInstruction.h | 233 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
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| H A D | DAGISelMatcherGen.cpp | 925 HandledReg = II.ImplicitDefs[0]; in EmitResultInstructionAsOperand()
1067 HandledReg = II.ImplicitDefs[0]; in EmitResultCode()
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| H A D | GlobalISelEmitter.cpp | 3097 if (!I->ImplicitDefs.empty() || !I->ImplicitUses.empty()) { in emitActionOpcodes()
3098 for (auto Def : I->ImplicitDefs) { in emitActionOpcodes()
3613 const std::vector<Record *> &ImplicitDefs) const;
4959 const std::vector<Record *> &ImplicitDefs) const { in importImplicitDefRenderers()
4960 if (!ImplicitDefs.empty()) in importImplicitDefRenderers()
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| H A D | CodeGenDAGPatterns.cpp | 2526 if (!InstInfo.ImplicitDefs.empty()) { in ApplyTypeConstraints()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/ |
| H A D | MCInstrDesc.cpp | 35 if (const MCPhysReg *ImpDefs = ImplicitDefs) in hasImplicitDefOfPhysReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 1939 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_r()
1963 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rr()
1989 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrr()
2011 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_ri()
2035 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rii()
2054 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_f()
2079 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rri()
2095 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_i()
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| H A D | ScheduleDAGFast.cpp | 433 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
512 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
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| H A D | ScheduleDAGRRList.cpp | 1284 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
1425 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMux.cpp | 163 if (const MCPhysReg *R = D.ImplicitDefs) in getDefsUses()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 314 .addReg(II.ImplicitDefs[0])); in fastEmitInst_r()
341 .addReg(II.ImplicitDefs[0])); in fastEmitInst_rr()
366 .addReg(II.ImplicitDefs[0])); in fastEmitInst_ri()
385 .addReg(II.ImplicitDefs[0])); in fastEmitInst_i()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 1203 if (MCID.ImplicitDefs) in verifyImplicitOperands()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 3978 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrrr()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2708 if (NewDesc.ImplicitDefs) in optimizeCompareInstr()
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/ |
| H A D | CodeGenerator.rst | 1319 ``TargetInstrInfo::get(opcode)::ImplicitDefs``, where ``opcode`` is the opcode
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