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Searched refs:ImplicitDefine (Results 1 – 25 of 29) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp172 .addReg(TargetReg, RegState::ImplicitDefine); in buildGitPtr()
549 .addReg(ScratchRsrcReg, RegState::ImplicitDefine) in emitEntryFunctionScratchRsrcRegSetup()
583 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
598 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
609 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
613 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
619 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
623 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
650 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
654 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
H A DSIRegisterInfo.cpp195 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
206 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
1173 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1219 AccRead.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1250 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1340 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillSGPR()
1427 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
1454 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
H A DSILowerControlFlow.cpp228 .addReg(Exec, RegState::ImplicitDefine); in emitIf()
H A DSIInstrInfo.cpp1823 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
1857 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp236 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in convertToBRCT()
682 RegState::ImplicitDefine | RegState::Dead); in fuseCompareOperations()
H A DSystemZShortenInst.cpp147 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in shortenOn001AddCC()
H A DSystemZFrameLowering.cpp308 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
H A DSystemZInstrInfo.cpp223 .addReg(Reg64, RegState::ImplicitDefine); in expandLoadStackGuard()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h63 ImplicitDefine = Implicit | Define, enumerator
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp536 .addReg(Reg, RegState::ImplicitDefine) in ExpandMOVEM()
H A DM68kFrameLowering.cpp891 I.addReg(Info.getReg(), RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp243 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
H A DARMFrameLowering.cpp1481 .addReg(SupReg, RegState::ImplicitDefine) in emitAlignedDPRCS2Restores()
1498 .addReg(SupReg, RegState::ImplicitDefine) in emitAlignedDPRCS2Restores()
H A DARMExpandPseudoInsts.cpp627 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
795 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
2528 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
H A DARMBaseInstrInfo.cpp1429 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1475 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1499 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1519 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
H A DARMLoadStoreOptimizer.cpp958 MIB.addReg(ImpDef, RegState::ImplicitDefine); in MergeOpsUpdate()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp2139 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr()
2140 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()
H A DMipsSEInstrInfo.cpp134 .addReg(DestReg, RegState::ImplicitDefine); in copyPhysReg()
H A DMipsSEISelDAGToDAG.cpp57 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef; in addDSPCtrlRegOperands()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2171 .addReg(Pred[1].getReg(), RegState::ImplicitDefine); in PredicateInstruction()
2194 .addReg(Pred[1].getReg(), RegState::ImplicitDefine); in PredicateInstruction()
2251 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine); in PredicateInstruction()
3180 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine); in replaceInstrWithLI()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp999 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | in EmitMachineNode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp4700 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
4729 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
4804 MIB.addReg(Reg, RegState::ImplicitDefine); in expandPostRAPseudo()
5267 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
5276 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DMIRLangRef.rst550 - ``RegState::ImplicitDefine``
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp1391 Flags |= RegState::ImplicitDefine; in parseRegisterFlag()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2438 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); in emitSjLjDispatchBlock()

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