| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrFormats.td | 74 class I_16_ZX<string op, ImmLeaf ImmType, list<dag> pattern>
76 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
88 class I_16_MOV<bits<5> sop, string op, ImmLeaf ImmType>
89 : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), (ins ImmType:$imm16),
91 [(set GPR:$rz, ImmType:$imm16)]> {
204 class I_12<bits<4> sop, string op, SDNode node, ImmLeaf ImmType>
206 (ins GPR:$rx, ImmType:$imm12), !strconcat(op, "\t$rz, $rx, $imm12"),
207 [(set GPR:$rz, (node GPR:$rx, ImmType:$imm12))]> {
256 class I_5_ZX<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
259 (ins GPR:$false, GPR:$rx, ImmType:$imm5),
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrFormats.td | 80 // ImmType - This specifies the immediate type used by an instruction. This is
83 class ImmType<bits<4> val> {
86 def NoImm : ImmType<0>;
87 def Imm8 : ImmType<1>;
88 def Imm8PCRel : ImmType<2>;
89 def Imm8Reg : ImmType<3>; // Register encoded in [7:4].
90 def Imm16 : ImmType<4>;
91 def Imm16PCRel : ImmType<5>;
92 def Imm32 : ImmType<6>;
93 def Imm32PCRel : ImmType<7>;
[all …]
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| H A D | X86InstrArithmetic.td | 540 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
568 ImmType ImmEncoding = immkind;
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | FastISel.h | 369 MVT ImmType);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoVPseudos.td | 1584 multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
1586 defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
1792 multiclass VPseudoBinaryV_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
1795 defm "" : VPseudoBinaryV_VI<ImmType, Constraint>;
1808 multiclass VPseudoBinaryV_VX_VI<Operand ImmType = simm5> {
1810 defm "" : VPseudoBinaryV_VI<ImmType>;
1925 multiclass VPseudoTernaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
1927 defm _VI : VPseudoTernary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
1957 multiclass VPseudoTernaryV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
1959 defm "" : VPseudoTernaryV_VI<ImmType, Constraint>;
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| H A D | RISCVInstrInfoVSDPatterns.td | 154 Operand ImmType = simm5>
160 !cast<ComplexPattern>(SplatPat#_#ImmType),
161 ImmType>;
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| H A D | RISCVInstrInfoVVLPatterns.td | 312 Operand ImmType = simm5>
318 !cast<ComplexPattern>(SplatPat#_#ImmType),
319 ImmType>;
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| H A D | RISCVInstrInfo.td | 866 class PatGprImm<SDPatternOperator OpNode, RVInst Inst, ImmLeaf ImmType>
867 : Pat<(XLenVT (OpNode (XLenVT GPR:$rs1), ImmType:$imm)),
868 (Inst GPR:$rs1, ImmType:$imm)>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXIntrinsics.td | 1703 NVPTXRegClass regclass, Operand ImmType,
1718 (ins Int32Regs:$src, ImmType:$b),
1721 (ins Int64Regs:$src, ImmType:$b),
1726 NVPTXRegClass regclass, Operand ImmType,
1740 (ins Int32Regs:$src, ImmType:$b, regclass:$c),
1743 (ins Int64Regs:$src, ImmType:$b, regclass:$c),
1746 (ins Int32Regs:$src, regclass:$b, ImmType:$c),
1749 (ins Int64Regs:$src, regclass:$b, ImmType:$c),
1753 (ins Int32Regs:$src, ImmType:$b, ImmType:$c),
1756 (ins Int64Regs:$src, ImmType:$b, ImmType:$c),
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 1861 uint64_t Imm, MVT ImmType) { in fastEmit_ri_() argument
1882 Register MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm); in fastEmit_ri_()
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/TableGen/ |
| H A D | index.rst | 139 ImmType ImmT = NoImm;
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| H A D | ProgRef.rst | 1952 ImmType ImmT = NoImm;
|