| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 23 #ifndef INSTRUCTION
24 #define INSTRUCTION(N,A,R,I)
27 // DAG_INSTRUCTION is treated like an INSTRUCTION if the DAG node isn't used.
29 #define DAG_INSTRUCTION(N,A,R,I,D) INSTRUCTION(N,A,R,I)
34 #define FUNCTION(N,A,R,I) INSTRUCTION(N,A,R,I)
103 #undef INSTRUCTION
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX1011.rst | 41 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
51 …**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS…
61 **INSTRUCTION** **DST** **SRC0** **SRC1**
71 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
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| H A D | AMDGPUAsmGFX906.rst | 41 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
54 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
64 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
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| H A D | AMDGPUAsmGFX908.rst | 41 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
51 …**INSTRUCTION** **SRC0** **SRC1** **SRC2** **SRC3** …
61 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
83 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
93 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
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| H A D | AMDGPUAsmGFX904.rst | 41 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
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| H A D | AMDGPUAsmGFX900.rst | 41 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
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| H A D | AMDGPUAsmGFX7.rst | 39 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
186 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3*…
195 …**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIER…
249 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** *…
346 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIER…
362 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **…
426 **INSTRUCTION** **DST** **SRC0** **SRC1**
447 **INSTRUCTION** **DST** **SRC**
503 **INSTRUCTION** **DST** **SRC0** **SRC1**
554 **INSTRUCTION** **SRC0** **SRC1**
[all …]
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| H A D | AMDGPUAsmGFX10.rst | 39 …**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS…
145 …**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2…
251 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
413 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3*…
422 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
558 **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
671 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODI…
695 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** …
775 …**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIER…
1002 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
[all …]
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| H A D | AMDGPUAsmGFX8.rst | 39 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
191 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3*…
200 …**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIER…
248 **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
345 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODI…
369 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** …
436 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **…
468 **INSTRUCTION** **DST** **SRC**
525 **INSTRUCTION** **DST** **SRC0** **SRC1**
577 **INSTRUCTION** **SRC0** **SRC1**
[all …]
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| H A D | AMDGPUAsmGFX9.rst | 39 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
201 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3*…
210 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
336 **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
433 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODI…
457 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** …
534 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
626 **INSTRUCTION** **DST** **SRC**
688 **INSTRUCTION** **DST** **SRC0** **SRC1**
749 **INSTRUCTION** **SRC0** **SRC1**
[all …]
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| H A D | AMDGPUAsmGFX90a.rst | 39 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
171 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
305 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFI…
338 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MO…
362 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** …
446 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
538 **INSTRUCTION** **DST** **SRC**
600 **INSTRUCTION** **DST** **SRC0** **SRC1**
661 **INSTRUCTION** **SRC0** **SRC1**
689 **INSTRUCTION** **DST** **SRC0** **SRC1**
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/IR/ |
| H A D | IntrinsicInst.cpp | 255 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in isUnaryOp() macro
266 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in isTernaryOp() macro
275 #define INSTRUCTION(NAME, NARGS, ROUND_MODE, INTRINSIC) \ in classof() macro
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| H A D | IRBuilder.cpp | 860 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in CreateConstrainedFPCast() macro
919 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in CreateConstrainedFPCall() macro
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| H A D | Function.cpp | 447 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in isConstrainedFPIntrinsic() macro
451 #undef INSTRUCTION in isConstrainedFPIntrinsic()
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| H A D | Verifier.cpp | 4684 #define INSTRUCTION(NAME, NARGS, ROUND_MODE, INTRINSIC) \ in visitIntrinsicCall() macro
5321 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in visitConstrainedFPIntrinsic() macro
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| /netbsd-src/sys/arch/m68k/fpsp/ |
| H A D | stan.sa | 335 *--THE REMAINDER INSTRUCTION WHICH IS NOW IN SOFTWARE.
408 *--HIDE SIX CYCLES OF INSTRUCTION
421 *--HIDE 4 CYCLES OF INSTRUCTION; creating 2**(L)*Piby2_1 and 2**(L)*Piby2_2
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| H A D | ssin.sa | 405 *--THE REMAINDER INSTRUCTION WHICH IS NOW IN SOFTWARE.
477 *--HIDE SIX CYCLES OF INSTRUCTION
490 *--HIDE 4 CYCLES OF INSTRUCTION; creating 2**(L)*Piby2_1 and 2**(L)*Piby2_2
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kInstrFormats.td | 335 // M68k INSTRUCTION. Most instructions specify the location of an operand by
367 // M68k PSEUDO INSTRUCTION
|
| /netbsd-src/sys/arch/m68k/fpe/ |
| H A D | README | 102 4. HOW TO ADD A NEW INSTRUCTION SUPPORT
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsInstrFormats.td | 12 // CPU INSTRUCTION FORMATS
666 // FLOATING POINT INSTRUCTION FORMATS
|
| H A D | Mips16InstrFormats.td | 12 // CPU INSTRUCTION FORMATS
|
| /netbsd-src/external/gpl3/gdb/dist/sim/microblaze/ |
| H A D | ChangeLog-2021 | 106 (INSTRUCTION): Likewise.
|
| /netbsd-src/external/lgpl3/gmp/dist/mpn/x86/ |
| H A D | README | 212 IMUL INSTRUCTION
|
| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/i386/ |
| H A D | ppro.md | 47 ;; INSTRUCTION POOL __________|_______/
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/config/i386/ |
| H A D | ppro.md | 47 ;; INSTRUCTION POOL __________|_______/
|