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Searched refs:INSERT_VECTOR_ELT (Results 1 – 25 of 35) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp186 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
187 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
188 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
189 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
253 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in R600TargetLowering()
453 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
714 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
1798 case ISD::INSERT_VECTOR_ELT: { in PerformDAGCombine()
H A DSIISelLowering.cpp256 case ISD::INSERT_VECTOR_ELT: in SITargetLowering()
285 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
286 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
299 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
300 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v8i32); in SITargetLowering()
313 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
314 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v16i32); in SITargetLowering()
327 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
328 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v32i32); in SITargetLowering()
344 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom); in SITargetLowering()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h494 INSERT_VECTOR_ELT, enumerator
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp1061 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
1094 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
1102 ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
H A DREADME_ALTIVEC.txt314 Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only
H A DPPCISelLowering.cpp809 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in PPCTargetLowering()
892 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in PPCTargetLowering()
1141 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in PPCTargetLowering()
1142 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in PPCTargetLowering()
1242 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in PPCTargetLowering()
1243 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in PPCTargetLowering()
1255 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); in PPCTargetLowering()
10487 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && in LowerINSERT_VECTOR_ELT()
10837 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp435 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); in ExpandOp_INSERT_VECTOR_ELT()
439 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); in ExpandOp_INSERT_VECTOR_ELT()
H A DLegalizeVectorTypes.cpp57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
926 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; in SplitVectorResult()
1576 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in SplitVecRes_INSERT_VECTOR_ELT()
1580 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, in SplitVecRes_INSERT_VECTOR_ELT()
2985 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; in WidenVectorResult()
3233 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, in CollectOpsToWiden()
4005 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), in WidenVecRes_INSERT_VECTOR_ELT()
5080 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem, in WidenVecOp_VECREDUCE()
5105 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem, in WidenVecOp_VECREDUCE_SEQ()
5234 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], in BuildVectorFromScalar()
H A DSelectionDAGDumper.cpp284 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; in getOperationName()
H A DLegalizeDAG.cpp2993 case ISD::INSERT_VECTOR_ELT: in ExpandNode()
4379 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) { in PromoteNode()
4837 case ISD::INSERT_VECTOR_ELT: { in PromoteNode()
4880 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT, in PromoteNode()
H A DLegalizeIntegerTypes.cpp105 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerResult()
1493 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerOperand()
4196 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; in ExpandIntegerOperand()
4880 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT, in PromoteIntRes_INSERT_VECTOR_ELT()
/netbsd-src/external/apache2/llvm/dist/llvm/utils/
H A Dupdate_mir_test_checks.py258 INSERT_VECTOR_ELT='IVEC',
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEISelLowering.cpp297 setOperationAction(ISD::INSERT_VECTOR_ELT, LegalVecVT, Legal); in initVPUActions()
312 setOperationAction(ISD::INSERT_VECTOR_ELT, LegalPackedVT, Custom); in initVPUActions()
1652 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), AccuV, in lowerBUILD_VECTOR()
1717 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
2786 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!"); in lowerINSERT_VECTOR_ELT()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp422 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::i64, Custom); in RISCVTargetLowering()
443 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
494 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
561 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
640 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
674 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
750 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
1396 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntegerViaVecVT, Vec, in lowerBUILD_VECTOR()
1412 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntegerViaVecVT, Vec, Elt, in lowerBUILD_VECTOR()
1586 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Vec, V, in lowerBUILD_VECTOR()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp185 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) in WebAssemblyTargetLowering()
1244 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
1910 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane, in LowerBUILD_VECTOR()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp170 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
262 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
333 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom); in addMVEVectorTypes()
396 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
443 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
981 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in ARMTargetLowering()
2136 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
2150 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
4337 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue, in LowerFormalArguments()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp361 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
499 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in SystemZTargetLowering()
500 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in SystemZTargetLowering()
5133 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I], in buildVector()
5205 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, in lowerSCALAR_TO_VECTOR()
5235 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT, in lowerINSERT_VECTOR_ELT()
5471 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
6413 if (Op.getOpcode() == ISD::INSERT_VECTOR_ELT && Op.hasOneUse()) { in combineBSWAP()
6438 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VecVT, in combineBSWAP()
H A DSystemZISelDAGToDAG.cpp1621 case ISD::INSERT_VECTOR_ELT: { in Select()
H A DSystemZOperators.td304 def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp122 setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom); in initializeHVXLowering()
226 setOperationAction(ISD::INSERT_VECTOR_ELT, BoolV, Custom); in initializeHVXLowering()
2103 case ISD::INSERT_VECTOR_ELT: return LowerHvxInsertElement(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1647 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, in HexagonTargetLowering()
1696 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom); in HexagonTargetLowering()
3139 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp329 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAIntType()
383 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAFloatType()
1962 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2525 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, in lowerBUILD_VECTOR()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp908 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in AArch64TargetLowering()
1378 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
1519 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForFixedLengthSVE()
4554 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
9141 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerVECTOR_SHUFFLE()
9955 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); in LowerBUILD_VECTOR()
9982 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, NewVector, in LowerBUILD_VECTOR()
10025 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
10050 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!"); in LowerINSERT_VECTOR_ELT()
10079 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec, in LowerINSERT_VECTOR_ELT()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td445 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
676 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp825 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in X86TargetLowering()
970 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in X86TargetLowering()
971 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in X86TargetLowering()
972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in X86TargetLowering()
1003 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1174 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in X86TargetLowering()
1419 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1501 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1732 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1872 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
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