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Searched refs:GraphicsLevel (Results 1 – 18 of 18) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_tonga_smumgr.c700 offsetof(SMU72_Discrete_DpmTable, GraphicsLevel); in tonga_populate_all_graphic_levels()
705 SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; in tonga_populate_all_graphic_levels()
718 &(smu_data->smc_state_table.GraphicsLevel[i])); in tonga_populate_all_graphic_levels()
724 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in tonga_populate_all_graphic_levels()
728 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in tonga_populate_all_graphic_levels()
732 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in tonga_populate_all_graphic_levels()
746 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = in tonga_populate_all_graphic_levels()
776 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; in tonga_populate_all_graphic_levels()
779 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; in tonga_populate_all_graphic_levels()
782 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; in tonga_populate_all_graphic_levels()
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H A Damdgpu_iceland_smumgr.c970 offsetof(SMU71_Discrete_DpmTable, GraphicsLevel); in iceland_populate_all_graphic_levels()
975 SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; in iceland_populate_all_graphic_levels()
988 &(smu_data->smc_state_table.GraphicsLevel[i])); in iceland_populate_all_graphic_levels()
994 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in iceland_populate_all_graphic_levels()
998 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in iceland_populate_all_graphic_levels()
1002 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels()
1032 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; in iceland_populate_all_graphic_levels()
1036 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; in iceland_populate_all_graphic_levels()
1039 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; in iceland_populate_all_graphic_levels()
H A Damdgpu_polaris10_smumgr.c151 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); in polaris10_setup_graphics_level_structure()
993 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); in polaris10_populate_all_graphic_levels()
997 smu_data->smc_state_table.GraphicsLevel; in polaris10_populate_all_graphic_levels()
1010 &(smu_data->smc_state_table.GraphicsLevel[i])); in polaris10_populate_all_graphic_levels()
1020 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; in polaris10_populate_all_graphic_levels()
1022 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in polaris10_populate_all_graphic_levels()
2475 smu_data->smc_state_table.GraphicsLevel; in polaris10_update_dpm_settings()
2477 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); in polaris10_update_dpm_settings()
H A Damdgpu_fiji_smumgr.c256 level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel); in fiji_setup_graphics_level_structure()
1018 offsetof(SMU73_Discrete_DpmTable, GraphicsLevel); in fiji_populate_all_graphic_levels()
1022 smu_data->smc_state_table.GraphicsLevel; in fiji_populate_all_graphic_levels()
1753 GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1]. in fiji_populate_clock_stretcher_data_table()
1797 smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency); in fiji_populate_clock_stretcher_data_table()
2559 smu_data->smc_state_table.GraphicsLevel; in fiji_update_dpm_settings()
2561 offsetof(SMU73_Discrete_DpmTable, GraphicsLevel); in fiji_update_dpm_settings()
H A Damdgpu_ci_smumgr.c482 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); in ci_populate_all_graphic_levels()
486 smu_data->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
496 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
498 smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
502 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
2770 smu_data->smc_state_table.GraphicsLevel; in ci_update_dpm_settings()
2772 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); in ci_update_dpm_settings()
H A Damdgpu_vegam_smumgr.c877 offsetof(SMU75_Discrete_DpmTable, GraphicsLevel); in vegam_populate_all_graphic_levels()
881 smu_data->smc_state_table.GraphicsLevel; in vegam_populate_all_graphic_levels()
894 &(smu_data->smc_state_table.GraphicsLevel[i])); in vegam_populate_all_graphic_levels()
908 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; in vegam_populate_all_graphic_levels()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dsmu7_fusion.h235 SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE]; member
H A Dsmu7_discrete.h324 SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS]; member
H A Dradeon_ci_dpm.c3287 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); in ci_populate_all_graphic_levels()
3290 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3299 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3303 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3305 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3308 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
H A Dradeon_kv_dpm.c776 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel), in kv_upload_dpm_settings()
1788 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) + in kv_update_dfs_bypass_settings()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
H A Dsmu7_fusion.h235 SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE]; member
H A Dsmu7_discrete.h325 SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS]; member
H A Dsmu71_discrete.h272 SMU71_Discrete_GraphicsLevel GraphicsLevel [SMU71_MAX_LEVELS_GRAPHICS]; member
H A Dsmu74_discrete.h283 SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS]; member
H A Dsmu72_discrete.h267 SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS]; member
H A Dsmu73_discrete.h251 SMU73_Discrete_GraphicsLevel GraphicsLevel [SMU73_MAX_LEVELS_GRAPHICS]; member
H A Dsmu75_discrete.h289 SMU75_Discrete_GraphicsLevel GraphicsLevel [SMU75_MAX_LEVELS_GRAPHICS]; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_kv_dpm.c859 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel), in kv_upload_dpm_settings()
1852 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) + in kv_update_dfs_bypass_settings()