Searched refs:FPRegs (Results 1 – 7 of 7) sorted by relevance
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
H A D | SparcInstrVIS.td | 86 def FZEROS : VISInstD<0b001100001, "fzeros", FPRegs>; 88 def FONES : VISInstD<0b001111111, "fones", FPRegs>; 90 def FSRC1S : VISInst1<0b001110101, "fsrc1s", FPRegs>; 92 def FSRC2S : VISInst2<0b001111001, "fsrc2s", FPRegs>; 94 def FNOT1S : VISInst1<0b001101011, "fnot1s", FPRegs>; 96 def FNOT2S : VISInst2<0b001100111, "fnot2s", FPRegs>; 98 def FORS : VISInst<0b001111101, "fors", FPRegs>; 100 def FNORS : VISInst<0b001100011, "fnors", FPRegs>; 102 def FANDS : VISInst<0b001110001, "fands", FPRegs>; 104 def FNANDS : VISInst<0b001101111, "fnands", FPRegs>; [all …]
|
H A D | SparcInstrInfo.td | 475 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 498 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 525 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32, IIC_iu_or_fpu_instr>; 526 def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32, IIC_iu_or_fpu_instr>, 580 defm STF : Store<"st", 0b100100, store, FPRegs, f32>; 581 def STFArr : StoreASI<"st", 0b110100, store, FPRegs, f32>, 1133 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1135 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))], 1138 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 1140 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))], [all …]
|
H A D | SparcInstr64Bit.td | 329 def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 330 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 403 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2), 407 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2), 411 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2), 432 (outs FPRegs:$rd), (ins DFPRegs:$rs2), 434 [(set FPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 446 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 448 [(set DFPRegs:$rd, (SPftox FPRegs:$rs2))]>;
|
H A D | SparcInstrAliases.td | 32 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>; 55 (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>; 509 def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>; 514 def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
|
H A D | SparcRegisterInfo.td | 349 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>; 353 // The Low?FPRegs classes are used only for inline-asm constraints.
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 2076 SmallVector<CalleeSavedInfo, 18> FPRegs; in processFunctionBeforeFrameFinalized() local 2103 FPRegs.push_back(CSI[i]); in processFunctionBeforeFrameFinalized() 2142 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { in processFunctionBeforeFrameFinalized() 2143 int FI = FPRegs[i].getFrameIdx(); in processFunctionBeforeFrameFinalized()
|
/netbsd-src/external/apache2/llvm/dist/llvm/docs/ |
H A D | WritingAnLLVMBackend.rst | 529 ``FPRegs``, ``DFPRegs``, and ``IntRegs``. For all three register classes, the 530 first argument defines the namespace with the string "``SP``". ``FPRegs`` 538 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
|