| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 90 DAG_FUNCTION(pow, 2, 1, experimental_constrained_pow, FPOW)
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 863 FPOW, enumerator
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| H A D | BasicTTIImpl.h | 1592 ISDs.push_back(ISD::FPOW); in getTypeBasedIntrinsicInstrCost()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 268 case ISD::FPOW: return "fpow"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 107 case ISD::FPOW: R = SoftenFloatRes_FPOW(N); break; in SoftenFloatResult()
1223 case ISD::FPOW: ExpandFloatRes_FPOW(N, Lo, Hi); break; in ExpandFloatResult()
2254 case ISD::FPOW: in PromoteFloatResult()
2619 case ISD::FPOW: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 419 case ISD::FPOW: in LegalizeOp()
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| H A D | LegalizeDAG.cpp | 4066 Results.push_back(DAG.getNode(ISD::FPOW, SDLoc(Node), in ConvertNodeToLibcall()
4076 case ISD::FPOW: in ConvertNodeToLibcall()
4679 case ISD::FPOW: in PromoteNode()
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| H A D | LegalizeVectorTypes.cpp | 135 case ISD::FPOW: in ScalarizeVectorResult()
1024 case ISD::FPOW: in SplitVectorResult()
3039 case ISD::FPOW: in WidenVectorResult()
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| H A D | SelectionDAG.cpp | 4339 case ISD::FPOW: { in isKnownNeverNaN()
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| H A D | DAGCombiner.cpp | 1690 case ISD::FPOW: return visitFPOW(N); in visit()
14342 (!DAG.getTargetLoweringInfo().isOperationExpand(ISD::FPOW, VT) && in visitFPOW()
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| H A D | SelectionDAGBuilder.cpp | 5342 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS, Flags); in expandPow()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1648 setOperationAction(ISD::FPOW , MVT::f128, Expand); in SparcTargetLowering()
1649 setOperationAction(ISD::FPOW , MVT::f64, Expand); in SparcTargetLowering()
1650 setOperationAction(ISD::FPOW , MVT::f32, Expand); in SparcTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 349 setOperationAction(ISD::FPOW, VT, Expand); in AArch64TargetLowering()
425 setOperationAction(ISD::FPOW, MVT::f128, Expand); in AArch64TargetLowering()
564 setOperationAction(ISD::FPOW, MVT::f32, Expand); in AArch64TargetLowering()
565 setOperationAction(ISD::FPOW, MVT::f64, Expand); in AArch64TargetLowering()
576 setOperationAction(ISD::FPOW, MVT::f16, Promote); in AArch64TargetLowering()
577 setOperationAction(ISD::FPOW, MVT::v4f16, Expand); in AArch64TargetLowering()
578 setOperationAction(ISD::FPOW, MVT::v8f16, Expand); in AArch64TargetLowering()
967 setOperationAction(ISD::FPOW, MVT::v1f64, Expand); in AArch64TargetLowering()
1366 setOperationAction(ISD::FPOW, VT, Expand); in addTypeForNEON()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1594 ISD::FPOW, ISD::FCOPYSIGN}) { in HexagonTargetLowering()
1639 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2, in HexagonTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 109 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 368 setOperationAction(ISD::FPOW, VT, Expand); in addMVEVectorTypes()
843 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); in ARMTargetLowering()
864 setOperationAction(ISD::FPOW, MVT::v4f32, Expand); in ARMTargetLowering()
880 setOperationAction(ISD::FPOW, MVT::v2f32, Expand); in ARMTargetLowering()
1023 setOperationAction(ISD::FPOW, MVT::f64, Expand); in ARMTargetLowering()
1397 setOperationAction(ISD::FPOW, MVT::f64, Expand); in ARMTargetLowering()
1398 setOperationAction(ISD::FPOW, MVT::f32, Expand); in ARMTargetLowering()
1472 setOperationAction(ISD::FPOW, MVT::f16, Promote); in ARMTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 439 setOperationAction(ISD::FPOW, MVT::f32, Expand); in MipsTargetLowering()
440 setOperationAction(ISD::FPOW, MVT::f64, Expand); in MipsTargetLowering()
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| H A D | MipsSEISelLowering.cpp | 146 setOperationAction(ISD::FPOW, MVT::f16, Promote); in MipsSETargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 295 setOperationAction(ISD::FPOW, MVT::f32, Legal); in AMDGPUTargetLowering()
474 setOperationAction(ISD::FPOW, VT, Expand); in AMDGPUTargetLowering()
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| H A D | SIISelLowering.cpp | 406 setOperationAction(ISD::FPOW, MVT::f16, Promote); in SITargetLowering()
9368 case ISD::FPOW: in fp16SrcZerosHighBits()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 481 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 369 setOperationAction(ISD::FPOW , MVT::f64, Expand); in PPCTargetLowering()
374 setOperationAction(ISD::FPOW , MVT::f32, Expand); in PPCTargetLowering()
818 setOperationAction(ISD::FPOW, VT, Expand); in PPCTargetLowering()
1130 setOperationAction(ISD::FPOW, MVT::f128, Expand); in PPCTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 787 setOperationAction(ISD::FPOW , MVT::f32 , Expand); in X86TargetLowering()
788 setOperationAction(ISD::FPOW , MVT::f64 , Expand); in X86TargetLowering()
789 setOperationAction(ISD::FPOW , MVT::f80 , Expand); in X86TargetLowering()
790 setOperationAction(ISD::FPOW , MVT::f128 , Expand); in X86TargetLowering()
808 setOperationAction(ISD::FPOW, VT, Expand); in X86TargetLowering()
1999 ISD::FPOW, ISD::STRICT_FPOW, in X86TargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 469 setOperationAction(ISD::FPOW, VT, Expand); in SystemZTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 304 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP, in RISCVTargetLowering()
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