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Searched refs:FCR (Results 1 – 25 of 30) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/DebugInfo/CodeView/
H A DStringsAndChecksums.cpp72 const DebugSubsectionRecord &FCR) { in initializeChecksums() argument
73 assert(FCR.kind() == DebugSubsectionKind::FileChecksums); in initializeChecksums()
78 consumeError(OwnedChecksums->initialize(FCR.getRecordData())); in initializeChecksums()
/netbsd-src/sys/arch/powerpc/booke/dev/
H A Dpq3nandfcm.c132 lbc_write_4(sc->sc_obio, FCR, __SHIFTIN(command, FCR_CMD0)); in pq3nandfcm_command()
215 lbc_write_4(sc->sc_obio, FCR, len); in pq3nandfcm_read_buf()
245 lbc_write_4(sc->sc_obio, FCR, len); in pq3nandfcm_write_buf()
/netbsd-src/sys/arch/evbarm/stand/boot2440/
H A Ddm9000.c77 #define FCR 0x0a /* flow control */ macro
273 val = CSR_READ_1(l, FCR); in dm9k_init()
274 CSR_WRITE_1(l, FCR, val | FCR_FLCE); in dm9k_init()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/CodeView/
H A DStringsAndChecksums.h72 void initializeChecksums(const DebugSubsectionRecord &FCR);
/netbsd-src/external/gpl3/gcc/dist/gcc/config/csky/
H A Dcsky_insn_fpu.md29 VUNSPEC_GET_FCR ; Represent fetch of FCR content.
30 VUNSPEC_SET_FCR ; Represent assign of FCR content.
31 VUNSPEC_INS_FCR ; Represent insert of FCR content.
/netbsd-src/sys/arch/mmeye/mmeye/
H A Dmachdep.c571 #define FCR 2 macro
609 OUTP(FCR, 0x00); /* no FIFO mode */ in Init16550()
/netbsd-src/sys/arch/sandpoint/stand/altboot/
H A Dbrdsetup.c79 #define FCR 2 macro
1155 UART_WRITE(base, FCR, 0x00); in init_uart()
1159 UART_WRITE(base, FCR, 0x07); /* FIFO on, TXRX FIFO reset */ in init_uart()
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Dia64-ic.tbl78 mov-from-AR-FCR; IC:mov-from-AR-M[Field(ar3) == FCR]
147 mov-to-AR-FCR; IC:mov-to-AR-M[Field(ar3) == FCR]
H A Dia64-waw.tbl10 AR[FCR]; IC:mov-to-AR-FCR; IC:mov-to-AR-FCR; impliedF
H A Dia64-raw.tbl10 AR[FCR]; IC:mov-to-AR-FCR; br.ia, IC:mov-from-AR-FCR; impliedF
H A DChangeLog-2008382 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
/netbsd-src/external/gpl3/gdb/dist/opcodes/
H A Dia64-ic.tbl78 mov-from-AR-FCR; IC:mov-from-AR-M[Field(ar3) == FCR]
147 mov-to-AR-FCR; IC:mov-to-AR-M[Field(ar3) == FCR]
H A Dia64-waw.tbl10 AR[FCR]; IC:mov-to-AR-FCR; IC:mov-to-AR-FCR; impliedF
H A Dia64-raw.tbl10 AR[FCR]; IC:mov-to-AR-FCR; br.ia, IC:mov-from-AR-FCR; impliedF
H A DChangeLog-2008382 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
/netbsd-src/external/gpl3/gdb.old/dist/opcodes/
H A Dia64-ic.tbl78 mov-from-AR-FCR; IC:mov-from-AR-M[Field(ar3) == FCR]
147 mov-to-AR-FCR; IC:mov-to-AR-M[Field(ar3) == FCR]
H A Dia64-waw.tbl10 AR[FCR]; IC:mov-to-AR-FCR; IC:mov-to-AR-FCR; impliedF
H A Dia64-raw.tbl10 AR[FCR]; IC:mov-to-AR-FCR; br.ia, IC:mov-from-AR-FCR; impliedF
H A DChangeLog-2008382 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Dia64-ic.tbl78 mov-from-AR-FCR; IC:mov-from-AR-M[Field(ar3) == FCR]
147 mov-to-AR-FCR; IC:mov-to-AR-M[Field(ar3) == FCR]
H A Dia64-waw.tbl10 AR[FCR]; IC:mov-to-AR-FCR; IC:mov-to-AR-FCR; impliedF
H A Dia64-raw.tbl10 AR[FCR]; IC:mov-to-AR-FCR; br.ia, IC:mov-from-AR-FCR; impliedF
H A DChangeLog-2008382 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td197 def FCR#I : MipsReg<I, ""#I>;
421 def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
/netbsd-src/sys/arch/powerpc/include/booke/
H A De500reg.h800 #define FCR 0xE8 /* Flash Command Register */ macro

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