Searched refs:ExtendOpcode (Results 1 – 5 of 5) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 351 if (CurrentUse.ExtendOpcode == OpcodeForCandidate || in ChoosePreferredUse()
352 CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
365 CurrentUse.ExtendOpcode != TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
367 else if (CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT && in ChoosePreferredUse()
374 if (CurrentUse.ExtendOpcode == TargetOpcode::G_SEXT && in ChoosePreferredUse()
377 else if (CurrentUse.ExtendOpcode == TargetOpcode::G_ZEXT && in ChoosePreferredUse()
546 Builder.getTII().get(Preferred.ExtendOpcode == TargetOpcode::G_SEXT in applyCombineExtendingLoads()
548 : Preferred.ExtendOpcode == TargetOpcode::G_ZEXT in applyCombineExtendingLoads()
563 if (UseMI->getOpcode() == Preferred.ExtendOpcode || in applyCombineExtendingLoads()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 42 unsigned ExtendOpcode; // G_ANYEXT/G_SEXT/G_ZEXT member
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 12127 unsigned ExtendOpcode = Extend.getOpcode(); in performCommonVectorExtendCombine() local
12129 bool IsSExt = ExtendOpcode == ISD::SIGN_EXTEND || in performCommonVectorExtendCombine()
12130 ExtendOpcode == ISD::SIGN_EXTEND_INREG || in performCommonVectorExtendCombine()
12131 ExtendOpcode == ISD::AssertSext; in performCommonVectorExtendCombine()
12132 if (!IsSExt && ExtendOpcode != ISD::ZERO_EXTEND && in performCommonVectorExtendCombine()
12133 ExtendOpcode != ISD::AssertZext && ExtendOpcode != ISD::AND) in performCommonVectorExtendCombine()
17502 unsigned ExtendOpcode = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerFixedLengthVectorIntDivideToSVE() local
17503 SDValue Op0 = DAG.getNode(ExtendOpcode, dl, WidenedVT, Op.getOperand(0)); in LowerFixedLengthVectorIntDivideToSVE()
17504 SDValue Op1 = DAG.getNode(ExtendOpcode, dl, WidenedVT, Op.getOperand(1)); in LowerFixedLengthVectorIntDivideToSVE()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 47791 unsigned ExtendOpcode = Extend->getOpcode(); in combineToExtendCMOV() local
47808 if (VT != MVT::i16 && !(ExtendOpcode == ISD::SIGN_EXTEND && VT == MVT::i32)) in combineToExtendCMOV()
47814 if (TargetVT == MVT::i64 && ExtendOpcode != ISD::SIGN_EXTEND) in combineToExtendCMOV()
47817 CMovOp0 = DAG.getNode(ExtendOpcode, DL, ExtendVT, CMovOp0); in combineToExtendCMOV()
47818 CMovOp1 = DAG.getNode(ExtendOpcode, DL, ExtendVT, CMovOp1); in combineToExtendCMOV()
47825 Res = DAG.getNode(ExtendOpcode, DL, TargetVT, Res); in combineToExtendCMOV()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 9820 auto ExtendOpcode = AllAddOne ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in foldVSelectOfConstants() local
9821 SDValue ExtendedCond = DAG.getNode(ExtendOpcode, DL, VT, Cond); in foldVSelectOfConstants()
|