| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.h | 73 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
|
| H A D | WebAssemblyISelLowering.cpp | 679 bool WebAssemblyTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
680 EVT ExtT = ExtVal.getValueType(); in isVectorLoadExtDesirable()
681 EVT MemT = cast<LoadSDNode>(ExtVal->getOperand(0))->getValueType(0); in isVectorLoadExtDesirable()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 671 int64_t ExtVal = IsBool ? CI->getZExtValue() : CI->getSExtValue(); in lowerAsmOperandForConstraint() local
672 Ops.push_back(MachineOperand::CreateImm(ExtVal)); in lowerAsmOperandForConstraint()
|
| H A D | LegalizerHelper.cpp | 2829 auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg); in lowerStore() local
2835 auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt); in lowerStore()
2850 MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO); in lowerStore()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 2191 ZExtInst *ExtVal = dyn_cast<ZExtInst>(CI->getArgOperand(0)); in optimizeCallInst() local
2192 if (!ExtVal || !ExtVal->hasOneUse() || in optimizeCallInst()
2193 ExtVal->getParent() == CI->getParent()) in optimizeCallInst()
2196 ExtVal->moveBefore(CI); in optimizeCallInst()
2199 InsertedInsts.insert(ExtVal); in optimizeCallInst()
4294 Value *ExtVal = SExt; in promoteOperandForTruncAndAnyExt() local
4304 ExtVal = ZExt; in promoteOperandForTruncAndAnyExt()
4317 Instruction *ExtInst = dyn_cast<Instruction>(ExtVal); in promoteOperandForTruncAndAnyExt()
4324 return ExtVal; in promoteOperandForTruncAndAnyExt()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 448 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
|
| H A D | ARMISelLowering.cpp | 17441 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
17442 EVT VT = ExtVal.getValueType(); in isVectorLoadExtDesirable()
17447 if (auto *Ld = dyn_cast<MaskedLoadSDNode>(ExtVal.getOperand(0))) { in isVectorLoadExtDesirable()
17459 if (ExtVal->use_empty() || in isVectorLoadExtDesirable()
17460 !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode())) in isVectorLoadExtDesirable()
17463 SDNode *U = *ExtVal->use_begin(); in isVectorLoadExtDesirable()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 1048 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
|
| H A D | AArch64ISelLowering.cpp | 4082 bool AArch64TargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
4083 return ExtVal.getValueType().isScalableVector(); in isVectorLoadExtDesirable()
12755 uint64_t ExtVal = C->getZExtValue(); in performSVEAndCombine() local
12760 if ((ExtVal == 0xFF && EltTy == MVT::i8) || in performSVEAndCombine()
12761 (ExtVal == 0xFFFF && EltTy == MVT::i16) || in performSVEAndCombine()
12762 (ExtVal == 0xFFFFFFFF && EltTy == MVT::i32)) in performSVEAndCombine()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 2367 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, in LowerSTOREVector() local
2370 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal); in LowerSTOREVector()
2371 Ops.push_back(ExtVal); in LowerSTOREVector()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2677 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; } in isVectorLoadExtDesirable() argument
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 1968 SDValue ExtVal = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, in ExtendToInt64() local
1971 return ExtVal; in ExtendToInt64()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 4530 int64_t ExtVal = in LowerAsmOperandForConstraint() local
4533 DAG.getTargetConstant(Offset + ExtVal, SDLoc(C), MVT::i64)); in LowerAsmOperandForConstraint()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 5446 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT, in lowerINSERT_VECTOR_ELT() local
5460 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 31892 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
31893 if (isa<MaskedLoadSDNode>(ExtVal.getOperand(0))) in isVectorLoadExtDesirable()
31896 EVT SrcVT = ExtVal.getOperand(0).getValueType(); in isVectorLoadExtDesirable()
51624 int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? CST->getZExtValue() in LowerAsmOperandForConstraint() local
51626 Result = DAG.getTargetConstant(ExtVal, SDLoc(Op), MVT::i64); in LowerAsmOperandForConstraint()
|